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ADVANCE INFORMATION
MICRONAS
DDP 3310B Display and Deflection Processor
Edition July 9, 1999 6251-464-1AI
MICRONAS
DDP 3310B
Contents Page 4 4 5 5 6 6 6 6 6 7 8 8 9 9 9 10 10 12 12 12 13 13 15 16 16 16 17 18 18 18 19 19 19 20 20 20 20 21 21 21 22 34 Section 1. 1.1. 1.2. 1.3. 2. 2.1. 2.1.1. 2.1.2. 2.1.3. 2.1.4. 2.1.5. 2.1.6. 2.1.7. 2.1.8. 2.1.9. 2.1.10. 2.1.11. 2.2. 2.2.1. 2.2.2. 2.2.3. 2.2.4. 2.2.5. 2.3. 2.3.1. 2.3.2. 2.3.3. 2.3.4. 2.3.5. 2.3.6. 2.3.7. 2.3.8. 2.3.9. 2.3.10. 2.3.11. 2.3.12. 2.3.13. 3. 3.1. 3.2. 3.3. 3.3.1. Title Introduction Main Features System Architecture System Application Functional Description Display Part Input Interface Horizontal Scaler Luma Processing Dynamic Peaking Soft Limiter Chroma Input Chroma Interpolation Chroma Transient Improvement Inverse Matrix and Digital RGB Processing Picture Frame Generator Scan Velocity Modulation Analog Back-End Analog RGB Insertion Half-Contrast Control Fast-Blank Monitor CRT Measurement and Control Average Beam Current Limiter Synchronization and Deflection Deflection Processing Security Unit for H-Drive Soft Start/Stop of Horizontal Drive Horizontal Phase Adjustment Vertical Synchronization Vertical and East/West Deflection Vertical Zoom EHT Compensation Protection Circuitry Display Frequency Doubling General-purpose D/A Converter Clock and Reset Reset and Power-On Serial Interface I2C-Bus Interface I2C Control and Status Registers XDFP Control and Status Registers Scaler Adjustment
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Contents, continued Page 35 35 35 38 41 42 44 44 44 45 45 45 46 46 47 47 48 49 49 49 50 50 50 51 51 51 52 53 56 56 57 60 Section 4. 4.1. 4.2. 4.3. 4.4. 4.5. 4.6. 4.6.1. 4.6.2. 4.6.3. 4.6.4. 4.6.4.1. 4.6.4.2. 4.6.4.3. 4.6.4.4. 4.6.4.5. 4.6.4.6. 4.6.4.7. 4.6.4.8. 4.6.4.9. 4.6.4.10. 4.6.4.11. 4.6.4.12. 4.6.4.13. 4.6.4.14. 4.6.4.15. 4.6.4.16. 4.6.4.17. 4.6.4.18. 4.6.4.19. 5. 6. Title Specifications Outline Dimensions Pin Connections and Short Descriptions Pin Description Pin Configuration Pin Circuits Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions Recommended Crystal Characteristics Characteristics General Characteristics Line-locked Clock Inputs: LLC1, LLC2 Luma, Chroma Inputs Reset Input, Test Input Half-Contrast Input I2C-Bus Interface Horizontal and Vertical Sync Inputs and Clock and Freqency Select Pins Horizontal Flyback Input FIFO Control Signals PWM Outputs Horizontal Drive Output Vertical Protection Input Horizontal Safety Input Vertical and East/West D/A Converter Output Sense A/D Converter Input Analog RGB and Fast-Blank Inputs Analog RGB Outputs, D/A Converters Scan Velocity Modulation Output DAC Reference, Beam Current Safety Application Circuit Data Sheet History
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Display and Deflection Processor 1. Introduction The DDP 3310B is a single-chip digital Display and Deflection Processor designed for high-quality backend applications in 100/120-Hz TV sets with 4:3- or 16:9 picture tubes. The IC can be combined with members of the DIGIT 3000 IC family (VPC 32xx, TPU 3040), or it can be used with third-party products. The IC contains the entire digital video component and deflection processing and all analog interface components. Deflection processing
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- scan velocity modulation output - high-performance H/V deflection - EHT compensation for vertical / East/West - soft start/stop of H-Drive - vertical angle and bow - differential vertical output - vertical zoom via deflection - horizontal and vertical protection circuit - adjustable horizontal frequency for VGA/SVGA display Miscellaneous - selectable 4:1:1/4:2:2 YCrCb input - selectable 27/32-MHz line-locked clock input - crystal oscillator for horizontal protection - automatic picture tube adjustment (cutoff, whitedrive) - single 5-V power supply - hardware for simple 50/60-Hz to 100/120-Hz conversion (display frequency doubling) - two I2C-controlled PWM outputs - beam current limiter
1.1. Main Features Video processing - linear horizontal scaling (0.25 ... 4) - non-linear horizontal scaling "panoramavision" - dynamic peaking - soft limiter (gamma correction) - color transient improvement - programmable RGB matrix - picture frame generator - two analog RGB/Fast-Blank inputs
YCrCb 4:2:2/4:1:1 Line-locked Clock 27/32 MHz
Horizontal Scaler Clock Gen. I2C Interface
Y Features C Features
Digital RGB Matrix Picture Frame Generator
3 x DAC (10 Bit) Tube Control
Analog RGB Switch Scan Velocity Modulation
RGB Out 2xRGB/FB In SVM
SDA/SCL
PWM
Measurement ADC
H/V Deflection Security Unit
DACs Display Frequency Doubling
HDrive V & E/W FIFO Controlling
PWM 1&2 Fig. 1-1: Block diagram of the DDP 3310B
Sense Input
2H / 2V (1H/1V)
HFlyback
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ation is derived from a single 20.25-MHz crystal. An optional adaptive 2H/4H comb filter (VPC 32xx) performs Y/C separation for PAL and NTSC and all of their substandards. The VPC 32xxD and the CIP 3250A provide a highquality analog RGB interface with character insertion capability. This allows appropriate processing of external sources such as MPEG 2 set-top boxes in transparent (4:2:2) quality. Furthermore, it translates RGB/ Fast-Blank signals to the common digital video bus and makes those signals available for 100-Hz processing. In some European countries (Italy), this feature is mandatory. The IP indicates memory-based image processing, such as scan rate conversion, vertical processing (Zoom), or PAL+ reconstruction. Examples: - Europe: 15 kHz/ 50 Hz 32 kHz/100 Hz interlaced - US: 15 kHz/60 Hz 31 kHz/120 Hz non-interlaced Note: The DDP 3310B and the VPC 32xx families support memory-based applications through linelocked clocks, syncs, and data. The CIP 3250A may run either with the native DIGIT3000 clock but also with a line-locked clock system.
1.2. System Architecture The DDP 3310B is a mixed-signal IC containing the entire digital video component processing such as chroma transient improvement (CTI), adaptive luma peaking, and a non-linear `Panorama' aspect ratio conversion. All deflection related signals can be adapted to different scan rates. The analog section contains all analog interface components and an ADC, to compensate long term changes of the picture tube parameters and extreme high-tension effects. Fig. 1-1 shows the block diagram of the single-chip Display and Deflection Processor.
1.3. System Application Fig. 1-2 depicts several DDP applications. Since the DDP functions as a video back-end, it must be complemented with additional functionality to form a complete TV set. The VPC 32xx family processes all worldwide analog video signals (including the European PALplus) and allows non-linear Panorama aspect ratio conversion. Thus, 4:3 and 16:9 systems can easily be configured by software. The aspect ratio scaling is also used as a sample rate converter to provide a line-locked digital component output bus (YCrCb) compliant to ITU-R-601. All video processing and line-locked clock/data gener-
Scan Velocity Modulation
Fast Blank Mixing
RGB Saturation
Comb Filter
16:9 Video
VPC 32xxD CVBS RGB VPC 32xx CIP 3250A IP DDP 3310B H/V Defl. RGB CVBS VPC 32xx FIFO DDP 3310B H/V Defl.

PAL+ 100 Hz
RGB
Fig. 1-2: DDP 3310B applications
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2. Functional Description 2.1. Display Part The display part converts the digital YCrCb to analog RGB (see Fig. 2-7) and provides contrast and saturation adjustment. In case of YCrCb 4:1:1 an interpolation filter is used, which converts the digital input signal to YCrCb 4:2:2 standard. The 4:2:2 YCrCb signal is processed by the horizontal scaler. In the luminance processing path, a variety of features, such as dynamic peaking and soft limiting, are provided. In the chrominance path, the CrCb signals are converted to 4:4:4 format and filtered by a color transient improvement circuit. The YCrCb signal is converted by a programmable matrix to RGB color space. 2.1.2. Horizontal Scaler
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The scaler block allows linear or non-linear horizontal scaling of the digital input video signal in the range of 0.25 to 4. Non-linear scaling, also called "panorama vision", provides a geometrical distortion of the input picture. It is used to fit a picture with 4:3 format on a 16:9 screen by stretching the picture geometry at the borders. The inverse effect can be produced by the scaler, also. The scaler consists of a programmable decimation and interpolation filter and a 1/2H FIFO memory. A summary of scaler modes is given in Table 2-1. Table 2-1: Scaler modes
2.1.1. Input Interface The data inputs Y0...Y7 and C0...C7 are clocked with the external clock LLC2. The clock frequency is selectable for 27 or 32 MHz. A clock generator converts the different external line-locked clock rates to a common internal sample rate of appr. 40.5 MHz in order to provide a fix bandwidth for all digital filters. The horizontal scaler is used for conversion of scan rate and non-linear aspect ratio. The horizontal sync puls at the HS pin should be an active video signal, which is not vertically blanked. The input interface signals are - external clock (LLC2) - luma / chroma inputs (Y0...Y7 / C0...C7) - horizontal sync (HS) / vertical sync (VS, VS2)
Mode Panorama 4:3 16:9 Waterglass 16:9 4:3
Scale Factor nonlinear compr. nonlinear zoom
Description 4:3 source displayed on a16:9 tube, borders distorted Letterbox source (PAL+) displayed on a 4:3 tube, vertical overscan, borders distorted, no cropping sample rate conversion from external to internal pixel clock sample rate conversion from external to internal pixel clock
2740.5 MHz
1.5 linear 1.25 linear
32 40 MHz
2.1.3. Luma Processing The blacklevel of the input signal is assumed to be 16 (ITU-R standard). The luminance signal is multiplied by a factor between 0 and 2 subdivided into 64 steps. With a contrast adjustment of 32 (gain=1) the signal can be shifted by 100 % of its maximal amplitude with the digital brightness value. This is for adjustment of the headrooms for under- and overshoot. After the brightness addition, the negative going signals are limited to zero. It is desirable to keep a small positive offset with the signal to prevent undershoots produced by the peaking from being cut.
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The center frequency of the peaking filter is selectable from 2.5 MHz to 3.2 MHz. For S-VHS and for notch filter color decoding, the total system frequency responses for both PAL and NTSC are shown in Fig. 2-1 and Fig. 2-2. (All frequencies refer to a 50/60-Hz video signal).
2.1.4. Dynamic Peaking Especially with decoded composite signals and notch filter luminance separation as input signals, it is necessary to improve the luminance frequency characteristics. With transparent high-bandwidth signals, it is sometimes desirable to soften the image. In the DDP 3310B, the luma frequency response is improved by "dynamic" peaking. It adapts to the amplitude and the frequency of the input signal. Small AC amplitudes are sharpened while large AC amplitudes remain nearly unmodified. The dynamic range can be adjusted from -14 to +14 dB for small high-frequency signals. There is separate adjustment for signal overshoot and for signal undershoot. For large signals, the dynamic range is limited by a non-linear function that does not create any visible alias components. The peaking can be switched over to "softening" by inverting the peaking term by software.
dB 20 15 10 5 0 -5 -10 -15 -20 0 2 4 6 8 10 MHz
Fig. 2-1: Dynamic peaking frequency response
dB 20 15 10 5 0 -5 -10 -15 -20 0 dB 20 15 10 5 0 -5 -10 -15 -20 0 2 4 6 8 10 MHz 20 2 4 6 8 10 MHz 20 15
dB
CF= 2.5 MHz
CF= 3.2 MHz
10 5
S-VHS
0 -5 -10 -15 -20 0 dB 2 4 6 8 10 MHz
CF= 3.2 MHz
15 10 5
CF= 2.5 MHz
PAL/SECAM
0 -5 -10 -15 -20 0 dB 20 2 4 6 8 10 MHz
dB 20 15 10 5 0 -5 -10 -15 -20 0 2 4 6 8 10 MHz
CF= 3.2 MHz
15 10 5
CF= 2.5 MHz
NTSC
0 -5 -10 -15 -20 0 2 4 6 8 10 MHz
Fig. 2-2: Total frequency response for peaking filter and S-VHS, PAL, NTSC
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2.1.5. Soft Limiter The dynamic range of the processed luma signal must be limited to prevent the CRT from overload. An appropriate headroom for contrast, peaking, and brightness can be adjusted by the TV manufacturer according to the CRT characteristics. All signals above this limit will be "soft"-clipped. A characteristic diagram of the soft limiter is shown in Fig. 2-3. The total limiter consists of three parts: Part A includes adjustable tilt point and gain. The gain before the tilt value is 1. Above the tilt value, a part (0...15/16) of the input signal is subtracted from the input signal itself. Therefore, the gain is adjustable from 16/16 to 1/16, when the slope value varies from 0 to 15. The tilt value can be adjusted from 0 to 511. Part B has the same characteristics as part A. The subtracting part is also relative to the input signal, so the total differential gain will become negative if the sum of slope A and slope B is greater than 16 and the input signal is above the both tilt values (see characteristics). Finally, the output signal of the soft limiter will be clipped by a hard limiter adjustable from 256 to 511.
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Table 2-2: 4:1:1 Chroma format Pin Name 1 C7 C6 C5 C4 Cb17 Cb16 Cr17 Cr16 Pixel Number 2 Cb15 Cb14 Cr15 Cr14 3 Cb13 Cb12 Cr13 Cr12 4 Cb11 Cb10 Cr11 Cr10
Note: Cxy; x = pixel number, y = bit number
Table 2-3: 4:2:2 Chroma format Pin Name 1 C7 C6 C5 Cb17 Cb16 Cb15 Cb14 Cb13 Cb12 Cb11 Cb10 Pixel Number 2 Cr17 Cr16 Cr15 Cr14 Cr13 Cr12 Cr11 Cr10 3 Cb37 Cb36 Cb35 Cb34 Cb33 Cb32 Cb31 Cb30 4 Cr37 Cr36 Cr35 Cr34 Cr33 Cr32 Cr31 Cr30
2.1.6. Chroma Input The chroma input signal can either be YCrCb in 4:1:1 or in 4:2:2 format. For the digital signal processing, the time-multiplexed chroma samples will be demultiplexed and synchronized with the signal at the HS pin. The input formatter accepts either two's complement or binary offset code. Also, the delay can be adjusted within a range of 2 input clocks relative to the luma signal; this doesn't affect the chroma multiplex.
C4 C3 C2 C1 C0
Note: Cxy; x = pixel number, y = bit number
Output 511
Part A Slope A [0...15]
Part B 0 2 4 6 8 10 12
Hard limiter
Calculation example for the softlimiter input amplitude.
400
0 2 4 6 8 10 12 14
Y Input
16...235 (ITU-R 601) 16 (constant) 63 20 off
300
Range= 256...511 Black Level Contrast 14 Dig. Brightness Peaking Slope B [0...15]
200
Limiter input signal: 100 Tilt A [ 0...511] 0 0 100 200 300 400 500 600 700 800 900 Tilt B [0...511] (Yin-black level)x CTM/32`+BRM (235-16)x63/32 + 20 = 451 Limiter Input 1023
Fig. 2-3: Characteristics of soft limiter A and B and hard limiter
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2.1.7. Chroma Interpolation In case of YCrCb 4:1:1 input format, an interpolation filter is used which converts the digital input signal to 4:2:2 format. This filter runs with the incoming pixel clock frequency. The signal is passed to the scaler in YCrCb 4:2:2 format in order to convert the incoming pixel clock frequency (27/32 MHz) to the internal frequency (40.5/ 40 MHz). A linear phase interpolator is used to convert the chroma sampling rate from 4:2:2 to 4:4:4. The frequency response of the interpolator is shown in Fig. 2-4. All further processing is carried out at the full sampling rate.
0
dB
-10
-20
-30
-40
-50 0 4 8 12 16 20
MHz
Fig. 2-4: Frequency response of the chroma 4:2:2 to 4:4:4 interpolation filter
2.1.8. Chroma Transient Improvement The intention of this block is to enhance the chroma resolution. A correction signal is calculated by differentiation of the color difference signals. The differentiation can be selected according to the signal bandwidth, e.g. for PAL/NTSC/SECAM or digital component signals, respectively. The amplitude of the correction signal is adjustable. Small noise amplitudes in the correction signal are suppressed by an adjustable coring circuit. To eliminate "wrong colors", which are caused by over and undershoots at the chroma transition, the sharpened chroma signals are limited to a proper value automatically.
a)
Cr Cb input
t b)
Ampl.
t
2.1.9. Inverse Matrix and Digital RGB Processing
c)
Six multipliers in parallel perform the matrix multiplication to transform the Cr and Cb signals to R-Y, B-Y, and G-Y. The initialization values for the matrix are computed from the standard ITU-R (CCIR) matrix:
Cr out Cb out
R 1 0 1,402 Y = 1 -0,345 - 0,713 x Cb G B 1 1,773 0 Cr
The multipliers are also used to adjust color saturation and picture contrast. Since the multiplier allows 4 as the biggest coefficient, it is possible that the product of CTMxSATMxMxxM will be clipped, which causes wrong colors. SATLIM limits the product of contrast times saturation to allow a maximum oversaturation. The matrix computes:
a) CrCb input of DTI b) CrCb input + correction signal c) sharpened and limited CrCb Fig. 2-5: Digital color transient improvement
t
After adding the post-processed luma, the digital RGB signals are limited to 10 bits. Three multipliers are used to digitally adjust the white-drive and to implement an average beam current limiter. See also Section 2.2.4. "CRT Measurement and Control".
R MR1M MR2M 1 Cb + CTM x Y CTM SATM SATLIM ---------------G = MIN ------------ x --------------- , --------------------- x 64 x MG1M MG2M x 32 32 32 Cr 32 B MB1M MB2M
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2.1.10. Picture Frame Generator When the picture does not fill the total screen (height or width too small) it is surrounded with black areas. These areas (and more) can be colored with the picture frame generator. Another possibility is the insertion of a vertical and a horizontal stripe into the picture. This is done by switching over the RGB signal from the matrix to the signal from the frame color register. The width of each area (left, right, upper, lower) can be adjusted separately. The generator starts on the right, respectively lower side of the screen and stops on the left, respectively upper side of the screen. This means, it runs during horizontal, respectively vertical flyback.The color of the complete border can be stored in a programmable frame color register. The format is 3x4 bit RGB. The contrast can be adjusted separately. If the start value for the generator is larger than the stop value, the picture frame is inserted at the borders. If the start value is smaller than the stop value a vertical or horizontal stripe is inserted.
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2.1.11. Scan Velocity Modulation Picture tubes equipped with an appropriate yoke can use the Scan Velocity Modulation signal to vary the speed of the electron gun during the entire video scan line depending on its content. Transitions from dark to bright will first speed up and then slow down the scan; vice-versa for the opposite transition (see Fig. 2-6). The digital RGB input signal for the SVM is converted to Y in a simple matrix. Then the Y signal is differentiated by a filter of the transfer function 1-Z-N, where N is programmable from 1 to 6. With a coring some noise can be suppressed. This is followed by a gain adjustment and an adjustable limiter. The analog output signal is generated by an 8-bit D/A converter. The signal delay can be adjusted by 3.5 clocks in half-clock steps in respect to the analog RGB output signals. This is useful to adjust the different group delays of analog RGB amplifiers to the one for the SVM yoke current.
Ampl.
Beam Current
SVM Yoke Current
t Fig. 2-6: SVM signal wave form
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13.5/16 MHz
27/32 MHz Contrast Y Intpl. 4:4:4 Cr Cb
40.5/40.0 MHz dig. Bright. Peaking Soft Limiter CTI Y Cr Cb
digital/analog Scan. Vel. Mod. R,G,B Picture Frame Gen. DAC
Y
FIFO Intpl. 4:2:2 FIFO
Scaler 1 Scaler 1
FIFO FIFO
SVM
Scaler 2 Scaler 2
C rC b 4:2:2/4:1:1 Line-locked Clock 27/32 MHz
digital R,G,B RGB Matrix Saturation White-Dr. x BCL 3xDAC RGB 3xDAC int. Bright. xWhite-Drive
Cock Generator H&V Timing Display Frequency Doubling int. H/V
R,G,B
DAC cutoff
DAC black
RGB out FBL1/2 in RGB1 in RGB2 in
I2C Interface
XDFP - H-PLL2/3, flyback control and soft start/stop - vertical, E/W deflection with EHT compensation and vertical zoom - beam current limiter - cutoff & drive control loop 2xDAC H-Drive Gen. H/V Protection H-Flyb. Skew
3xDAC ext. Bright. xWhite-Drive R,G,B
FBL Prio Clamping Clamping
Clk Security
V, E/W
Measurement ADC
3xDAC ext. Contr. xWhite-drive xBCL
HDrive
H/V Prot.
H-Flyb
V & E/W
Sense
RSW1&2
Fig. 2-7: Detailed block diagram of the DDP 3310B
DDP 3310B
DDP 3310B
2.2. Analog Back-End The digital RGB signals are converted to analog RGB using three video digital to analog converters (DAC) with 10-bit resolution. The analog RGB-outputs are current outputs with current-sink characteristics. The maximum current drawn by the output stage is obtained with peak white RGB. Each RGB signal has two additional DAC's with 9-bit resolution to adjust analog brightness (40 % of the full RGB range) and cutoff / black level (60 % of the full RGB range). An additional fixed current is applied for the blanking level. In order to define accurate color on different CRT displays, you must exactly adjust what color the CRT phosphorous produces to display the color on screen. To have the same colors for the life of the display, a build-in automatic tube control loop checks and adjusts the black level on every field and white point every third field. The back-end allows insertion of two external analog RGB signals. The RGB signals are key-clamped and inserted into the main RGB by the Fast-Blank switch. The external RGB signals can be adjusted independently as regarding DC-level (brightness) and magnitude (contrast). An external Half-Contrast signal can be used to reduce the output current of the internal RGB outputs to 50 %. The controlling of the white-drive/analog brightness and also the external contrast and brightness adjustments is done via the internal processor.
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Table 2-4: RGB Input Selection
Input Signals FBLIN1 0 0 1 1 1 0 0 0 1 1 FBLIN2 0 1 0 1 1 0 0 1 0 1 I2C Settings FBPOL 0 0 0 0 0 1 1 1 1 1 FBPRIO x x x 0 1 0 1 x x x Video RGB input 2 RGB input 1 RGB input 1 RGB input 2 RGB input 1 RGB input 2 RGB input 1 RGB input 2 Video Analog RGB Outputs
Note: with following I2C settings FBFOH1 = FBFOH2 = FBFOL1 = FBFOL2 = 0
2.2.2. Half-Contrast Control Insertion of transparent text pages or OSD onto the video picture is often difficult to read, especially if the video contrast is high. The DDP 3310B allows contrast reduction of the video background by means of a HalfContrast input (HCS pin). This input can be supplied with a fast switching signal (similar to the Fast-Blank input), typically defining a rectangular box in which the video picture is displayed with reduced contrast. The analog RGB inputs are still displayed with full contrast.
2.2.1. Analog RGB Insertion The DDP 3310B allows insertion of two external analog RGB signals. Each RGB signal is key-clamped and inserted into the main RGB by the Fast-Blank switch. The selected external RGB input can be overlaid or underlaid to the digital picture. The external RGB signals can be adjusted independently as regards DC level (brightness) and magnitude (contrast). It depends on the Fast-Blank input signals and the programming of a number of I2C-register settings which analog RGB input is selected. Both Fast-Blank inputs must be either active-Low or active-High. All signals for analog RGB insertion (RIN1/2, GIN1/2, BIN1/2, FBLIN1/2, HCS) must be synchronized to the horizontal flyback, otherwise a horizontal jitter will be visible. The DDP 3310B has no means for timing correction of the analog RGB input signals.
HCSPOL
HCS # HCS intern
HCSEN
HCSFOH
Fig. 2-8: Half-Contrast switch logic
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2.2.4. CRT Measurement and Control The display processor is equipped with an 8/12-bit PDM-ADC for all picture tube measuring purposes. This MADC is connected to the SENSE input pin, the input range is 0 to 1.6V. Cutoff and white-drive current measurement are carried out with 8-bit resolution during the vertical blanking interval. The current range for cutoff measurement is set by connecting the resistor R1 to the SENSE input. Due to the fact of a 1:10 relation between cutoff and white-drive current, the range select 2 output (RSW2) becomes active for the white-drive measurement and connects R3 in parallel to R1, thus determining the correct current range. During the active picture, the MADC is used for the average beam current limiter with a 12-bit resolution. Again, a different measurement range is selected with active range select 1&2 outputs (RSW1&RSW2) connecting R2 in parallel to R3 and R1. See Fig. 2-10 and Fig. 2-11 for the corresponding timing. These measurements are typically done at the summation point of the picture tube cathode currents. Another method uses two different current measurements. The range switch 1 pin (RSW1) can be used as a second Sense input, selectable by software. In this case, the cutoff and white-drive currents are measured as before at the SENSE input. The active picture measurement can be done with the second Sense input (RSW1). The signal may come (via a proper interface) from the low end of the EHT coil (CRT anode current). In this case, the resistor R2 in Fig. 2-10 has to be removed.
2.2.3. Fast-Blank Monitor The presence of external analog RGB sources can be detected by means of a Fast-Blank monitor. The status of the selected Fast-Blank input can be monitored via an I2C register. There is a 2-bit information, giving static and dynamic indication of a Fast-Blank signal. The static bit is directly reading the Fast-Blank input line, whereas the dynamic bit is reading the status of a flip flop triggered by the negative edge of the FastBlank signal. With this monitor logic it is possible to detect if there is an external RGB source active and if it is a full-screen insertion or only a box. The monitor logic is connected directly to the FBLIN1 or FBLIN2 pin. Selection is done via I2C register.
FBFOH1
FBFOL1
FBPOL
FBPRIO
FBLIN1
# FastBlank int
FastBlank Monitor FBLIN2 #
FastBlank Selection
FBFOH2
FBFOL2
FBMON
Beam Current 2 Beam Current 1
Fig. 2-9: Fast-Blank selection logic
A D
SENSE
MADC
RSW1
R2 R3
RSW2
R1
Fig. 2-10: MADC range switch
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The picture tube measurement returns results on every field for: - cutoff R - cutoff G - cutoff B - white-drive R or G or B (sequentially) Thus, a cutoff control cycle for RGB requires one field only while a complete white-drive control cycle requires three fields. During cutoff and white-drive measurement the average beam current limiter function (see Section 2.2.5.) is switched off. The amplitude of the cutoff and white-drive measurement lines can be programmed separately with IBRM and WDRM (see Fig. 2-11). The start line for the tube measurement (cutoff red) can be programmed via I2C-bus (TML). The built-in control loop for cutoff and white-drive can operate in three different modes selected by CUT(WDR)_GAIN and CUT(WDR)_DIS. - The user control mode is selected by setting CUT(WDR)_GAIN = 0. In this mode the registers CUT(WDR)_R/G/B are used as direct control values for cutoff and drive using the whole 9-bit range. If the measurement lines are enabled (CUT(WDR)_DIS = 0) the user can read the measured cutoff & white drive values in the CUTOFF(WDRIVE)_R/G/B registers. An external software can now control the settings of the CUT(WDR)_R/G/B registers.
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- The automatic mode is selected by setting CUT(WDR)_GAIN > 0 and CUT(WDR)_DIS = 0. In this mode, the registers CUT(WDR)_R/G/B are used as reference for the measured values (CUTOFF(WDRIVE)_R/G/B). Due to the 8-bit resolution of the ADC, only 8 LSB can be used as reference values. The calculated error is used with a small hysteresis (1,5 %) to adjust cutoff and drive. The higher the loop gain (CUT(WDR)_GAIN), the smaller the time constant for the adjustment. - If the automatic mode was once enabled (CUT(WDR)_GAIN > 0), the control loop can be stopped by setting CUT(WDR)_DIS = 1. In this mode, the calculated cutoff and drive values will no longer be modified and the measurement lines are suppressed. Changes of the reference values (CUT(WDR)_R/G/B) have no effect. If one of the calculated red, green, or blue white-drive values exceeds its maximal possible value (WDR_R/ G/B>511), the white balance gets misadjusted. An automatic drive saturation avoidance prevents from this effect (WDR_SAT = 1) from occurring. If one drive value exceeds the maximum allowed threshold (MAX_WDR), the amplitude of the white-drive measurement line will be increased and decreased if one of them goes below the fixed threshold 475.
CUT_R + IBRM + WDRMxWDR_R CUT_R + IBRM WhiteDrive Cutoff R R
Black ROUT Ultra Black GOUT
CUT_G + IBRM
Cutoff G
CUT_B + IBRM Cutoff B
BOUT Active Resistors Measurement Lines
R1||R2||R3 R1 R1||R3 R1 R1||R2||R3
BCL VBSO
OFFSET TML
CUTOFF
WDR VBST
BCL
Fig. 2-11: MADC measurement timing
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DDP 3310B
2.2.5. Average Beam Current Limiter The average beam current limiter (BCL) works on both the digital YUV input and the inserted analog RGB signals by using either the sense input or the RSW1 input for the beam current measurement. The BCL uses a different filter to average the beam current during the active picture resulting in a 12-bit resolution. The filter bandwidth is approximately 4 kHz. The beam current limiter allows the setting of a threshold current, a gain and an additional time constant. If the beam current is above the threshold, the excess current is low-pass filtered with the according gain and time constant. The result is used to attenuate the RGB outputs by adjusting the white-drive multipliers for the internal (digital) RGB signals and the analog contrast multipliers for the analog RGB inputs, respectively. The lower limit of the attenuator is programmable, thus a minimum contrast can always be set. If the minimum contrast is reached, the brightness will be decreased down to a programmable minimum as well. Typical characteristics of the BCL for different loop gains are shown in Fig. 2-12; for this example the tube has been assumed to have square-law characteristics.
Beam Current
gain = 0 %
gain = 10 %
gain = 60 % Threshold gain = 90 %
Drive
Fig. 2-12: Beam current limiter characteristics: beam current output vs. drive
Micronas
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DDP 3310B
2.3. Synchronization and Deflection 2.3.1. Deflection Processing The deflection processing generates the signals for the horizontal and vertical drive (see Fig. 2-13). This block contains two numeric phase-locked loops and a security unit: - PLL2 generates the horizontal and vertical timing, e.g. blanking, clamping, and sync signals. Phase and frequency are synchronized by the incoming sync signals. - PLL3 adjusts the phase of the horizontal drive pulse and compensates for the delay of the horizontal output stage. - The security unit observes the H-Drive output signal. With an external 5-MHz reference clock, this unit controls the H-Drive "off time" and period. In case of an incorrect H-Drive signal the security unit generates a free-running H-Drive signal divided down from the 5-MHz reference clock. The DDP 3310B is able to synchronize various horizontal frequencies, even VGA frequencies. Allowed horizontal frequencies are listed in Table 2-5. The horizontal drive uses a high-voltage (8 V) open-drain output transistor.
ADVANCE INFORMATION
2.3.2. Security Unit for H-Drive The security unit observes the H-Drive output signal with an external 5-MHz reference clock. For different horizontal frequencies the security unit uses different ranges to control the H-Drive signal. Selecting a specific horizontal frequency via I2C-register HFREQ automatically switches to the corresponding security range. The control ranges are listed in Table 2-5. The window of the control range has to fit into a main control window which is selectable with the FREQSEL input pin. With a Low signal at this pin, the main control range is 28.8...34.4 s and with a High signal, the main control range is 25.6...29.2 s. This is to prevent malfunctions if the horizontal deflection stage is prepared for VGA frequencies. The Horizontal Drive Output can be forced to the High level during Flyback. This means, the falling edge of the drive pulse occurs at the earliest to the end of the flyback pulse. This function can be enabled via the I2C bus (EFLB).
H Flyback
PLL3
Phase Comparator & Low-Pass FIFORWR FIFOWR FIFORRD FIFORD HSYNC 1H or 2H
FIFO control
FREQSEL Horizontal Drive Generator Security Unit H Drive
DCO
Blanking, Clamping, etc.
E/W Correction
PWM 15-Bit
E/W Output
Display Timing Phase Comparator & Low-Pass
PLL2
Sawtooth DCO PWM 15-Bit
V+ Output V-
VSYNC 1 V or 2 V
Display Frequency Doubling
2H 2V
Vertical Reset
Clock & Control
Fig. 2-13: Deflection processing block diagram
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DDP 3310B
2.3.3. Soft Start/Stop of Horizontal Drive In order to increase the energy supply of the horizontal deflection stage smoothly, a soft start decreases the drive frequency from 55 kHz to 31.25 kHz within 85 ms. The High time tH is always 14.4 s. This means, the duty factor decreases from 79.2 % to 45 % (see Fig. 2-14). The soft stop is needed, when the protection circuitry wants to turn off the H-Drive. It has the inverse behavior of the soft start and ends with a High level at the HOUT Pin.
85 ms tH = 14.4 s T=1/55 kHz Fig. 2-14: Soft start with a duty factor of 14.4/32
... ... ...
tH = 14.4 s T = 1/31.25 kHz
Table 2-5: Allowed Horizontal Frequencies Supply Clock (MHz) 27 27 27 27 27 27 32 32 32 32 32 40.5 Pixels per Line Supply Clk 864 858 800 768 720 712 1024 944 912 852 844 1296 Main Clock (in MHz) 40.5 40.5 40.5 40.5 40.5 40.5 40.0 40.0 40.0 40.0 40.0 40.5 Pixels per line Main Clk 1296 1287 1200 1152 1080 1068 1280 1180 1140 1065 1055 1296 Horizontal Frequency (Hz) 31.24968 31.46853 33.750 35.15625 37.500 37.92135 31.24952 33.89776 35.08747 37.55869 37.91469 31.24968 Minimum H-Drive Period (in s) 29.60 29.60 28.80 27.80 25.60 25.60 29.60 28.80 27.80 25.60 25.60 29.60 Maximum H-Drive Period (in s) 34.40 34.40 30.60 29.20 28.00 28.00 34.40 30.60 29.20 28.00 28.00 34.40 HFREQ (I2C)
000 010 100 001 101 110 000 100 001 101 110 000
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DDP 3310B
2.3.4. Horizontal Phase Adjustment This section describes a simple way to get a correct horizontal frame position and clamp window for analog RGB insertion. 1. For a correct scaler function in panorama/waterglass mode, the digital input data should be centered to the active video input signal. 2. The clamping pulse for analog RGB insertion can be adjusted to the pedestal of the input signal with POFS2. 3. The horizontal raster position of the analog inserted RGB1/2 signal can be set to the desired frame position with POFS3. 4. The horizontal position of the digital RGB signal can be shifted to the left and right with NEWLIN. Following values allowed in respect to POFS2: - 90 < (POFS2+NEWLIN) - (ClkxSFIF) < 580 - Clk = 3 @ LLC2 = 27 MHz - Clk = 2.5 @ LLC2 = 32 MHz 5. Now the positioning of horizontal blanking and the picture frame generator can be done.
ADVANCE INFORMATION
recorder search mode when the number of lines per field does not comply with the standard, or if you want to use a common value of LPFD for PAL and NTSC (e.g.: LPFD = 290; VSYNCWIN = 54).
2.3.6. Vertical and East/West Deflection The calculations of the Vertical deflection and East/ West correction waveforms are done in the internal processor. They are described as polynomials in x, where x varies from -0.5xzoom to +0.5xzoom for one field. For zoom>1 the range is limited between -0.5 and +0.5. The vertical deflection waveform is calculated as follows (without EHT compensation):
V = vpos + ampl ( x + lin x + scorr x )
2 3
- - - -
VPOS AMPL LIN SCORR
defines the vertical raster position is the vertical raster amplitude (zoom1) is the linearity coefficient is the coefficient for S-correction
2.3.5. Vertical Synchronization The number of lines per field can be adjusted by software (LPFD). This number is used to calculate the vertical raster. The DDP synchronizes only to a vertical sync within a programmable detection window (LPFD VSYNCWIN). If there is no vsync, the DDP runs with maximum allowed lines and if the vertical frequency is to high, it runs with minimum allowed lines. The smaller the detection window, the slower the DDP gets synchronized to the incoming vertical sync. In case of an interlaced input signal, it is possible to display both fields at the same raster position by setting R_MODE to 1 or 2. An automatic field length adaptation can be selected (VA_MODE). In this case, the vertical raster will be calculated according to the counted number of lines per field instead from LPFD. This is useful for video
The vertical sawtooth signal will be generated from a differential current D/A converter and can drive a DC coupled power stage. In order to get a faster vertical retrace timing, the output current of the vertical D/Aconverter can be increased during the retrace for a programmable number of lines (FLYBL). The range between the end of the flyback and the beginning of the raster is also programmable (HOLDL). The East/West deflection waveform, generated from a single-ended D/A converter, is given with the equation:
E W = width + tcorr x + cush x + corner x
2 4
- - - - -
WIDTH TCORR CUSH CRNU CRNL
is a DC value for the picture width is the trapezoidal correction is the pincushion correction is the upper corner correction is the lower corner correction
Vertical Amplitude
-0.5
-0.3
-0.1
0.1
0.3
0.5
x
E / W Amplitude
-0.5
-0.3
-0.1
0.1
0.3
0.5
x
Fig. 2-15: Vertical and East/West deflection waveforms
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DDP 3310B
2.3.9. Protection Circuitry Picture tube and drive stage protection is provided through the following measurements: - Vertical protection input: this pin watches the vertical sawtooth signal. In every field the sawtooth must descend below the lower threshold A and ascend above the upper threshold B. In this case the protection flag is set (sawtooth o.k.). If an error occurs the protection flag is cleared. After approx. 10 fields with cleared flag, the RGB drive signals are blanked. The blanking is cancelled if the flag is set for 40 fields (see Fig. 2-17). - Drive shutoff during flyback: this feature can be selected by software (EFLB) - Safety input pin: This pin has two thresholds. The applied signal has to meet the following conditions: 1. threshold B must not be overshot
2.3.7. Vertical Zoom With vertical zoom, the DDP 3310B is able to display different aspect ratios of the source signal on tubes with 4:3 or 16:9 aspect ratio by adapting the corresponding raster.
Vertical Sawtooth Start Stop East/West Parabola
Normal Fig. 2-16: Vertical zoom
Zoom
2. threshold A has to be exceeded permanently or at least once per line otherwise the RGB signals are blanked . Both thresholds have a small hysteresis.
2.3.8. EHT Compensation The vertical deflection waveform can be scaled according to the average beam current. This is used to compensate the effects of electric high-tension changes due to beam current variations. EHT compensation for East/West deflection is done with an offset corresponding to the average beam current. The time constant of this process is freely programmable with a resolution of 18 bit. Both corrections can be enabled separately. The maximum scaling coefficient for vertical deflection is 1x and the maximum offset for East/ West is y, where x, y are adjustable from 0 to 0.25. The horizontal phase at the output HOUT can be influenced according to the average beam current in a range of 1.5 s.
Vert. Protection Flag 1 Accu
-1
~10 fields ~40 fields
Blanking t Fig. 2-17: Protection timing
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DDP 3310B
2.3.10. Display Frequency Doubling The DDP 3310B handles single or double vertical and horizontal input frequencies. The Display Frequency Doubling is used when single H/V frequencies are applied and a FIFO for video frequency doubling is used. In this mode it is mandatory to supply an active video signal to the HS pin, which is not vertical blanked. Three different raster modes are selectable via I2C bus: 2.3.12. Clock and Reset
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The DDP 3310B has the capability to accept different line-locked clock rates: 27, 32, and 40.5 MHz.This external clock rate is converted internally to a clock rate of 40.5 or 40 MHz by means of a PLL. Selection of external clock frequency is done with pins CM1 and CM0. See Table 2-6 for clock frequency selection. To ensure lock of PLL a reset pulse of at least 500 s must be applied after power-up. Table 2-6: Clock Frequency Selection
A A` B` B (reduced line flicker) A A B B (improved vertical resolution) A A B` B` (non-interlaced) A/B means field A/B in original raster position and A`/B` means field A/B in the opposite raster position. A minimum field length filter can be switched on (DFDFILT) to write only the smallest field length of the past up to four fields into the memory. This prevents readbefore-write errors in signals with a strong changing field length (e.g. VCR signals).
CM1 0 0 1
CM0 0 1 0
LLC2 27 MHz 32 MHz 40.5 MHz
2.3.13. Reset and Power-On The IC has its own voltage supervision to generate an internal reset during power on or when the supply voltage (VSUPD) goes below ~4.5V. Also, a clock supervision of the 5-MHz clock keeps the internal reset active until a proper clock signal is detected (e.g. three clock cycles with the correct period). When the reset pin RESQ or the internal reset becomes active, all counters and registers are set to zero. When the reset pins are released, the internal reset is still active for approximately 4 s. Then all registers are loaded with their default values listed in Table 3-3. This initialization takes about 100 s. During and after reset, the HOUT signal remains High until a soft start (see Section 2.3.3.) will be performed by setting RAMP_EN.
2.3.11. General-purpose D/A Converter There are two D/A converters realized as pulse width modulators. The resolution is 8 bit and the clock frequency is 20.25 MHz. The outputs are push-pull types. For a ripple-free output voltage, a first-order low-pass filter with a corner frequency <120 Hz should be applied. The D/A converters will be adjusted via I2Cbus. They can be used to adjust two DC voltages, for example for horizontal raster position, raster tilt, or just as switching outputs when the values 0 and 255 are selected.
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DDP 3310B
3.2. I2C Control and Status Registers The I2C-bus interface uses one level of subaddress. First, the bus address selects the IC, then a subaddress selects one of the internal registers. They have 8- or 16-bit data size; 16-bit registers are accessed by reading/writing two 8-bit data words. - Writing is done by sending the device address first followed by the subaddress byte and one or two data bytes. - For reading, the read address has to be transmitted first by sending the device write address, followed by the subaddress, a second start condition with the device read address, and reading one or two bytes of data. Fig. 3-2 shows I2C protocol for read and write operations; the read operation requires an extra start condition and repetition of the chip address with read command set. Table 3-2 gives definitions of the I2C control and status registers.
3. Serial Interface 3.1. I2C-Bus Interface Communication between the DDP 3310B and the external controller is done via I2C-bus. The DDP 3310B has an I2C-bus slave interface and uses I2C clock synchronization to slow down the interface if required. Basically, there are two classes of registers in the DDP 3310B: 1. The first class are directly addressable I2C registers. They are embedded in the hardware. These registers are 8 or 16 bit wide. 2. The second class are "XDFP-REGISTERS", which are used by the "XDFP" on-chip controller. These registers are all 16 bit wide and read- and writable. Communication with these registers requires I2C packets with a 16-bit XDFP-register address and 16-bit data. Communication with both classes of registers (I2C and XDFP-REGISTERS) are performed via I2C; but the format of the I2C telegram depends on which type of register is being accessed. The I2C-bus chip address of the DDP 3310B is given below: A6 1 A5 0 A4 0 A3 0 A2 1 A1 0 A0 1 R/W 1/0
SDA SCL S
1 0
P
S P
= I2C-Bus Start Condition = I2C-Bus Stop Condition
Fig. 3-1: I2C-Bus protocol (MSB first, data must be stable while clock is High)
Write to I2C Control Register : S 1000 101 W Ack Sub-Addr. Ack 1- or 2-Byte Data Ack Read from I2C Control Register : S 1000 101 W Ack W = 0 (Write Bit) R = 1 (Read Bit) Sub-Addr. Ack S S = Start Condition P = Stop Condition 1000 101 R Ack High-Byte Data Ack Low-Byte Data Nak P P
Ack = 0 (Acknowledge Bit from DDP 3310B=gray or controller=hatched) Nak = 1 (Not Acknowledge Bit from controller=hatched or indicating an error state from DDP 3310B=gray)
Fig. 3-2: I2C-Bus protocol
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DDP 3310B
3.3. XDFP Control and Status Registers The second class are "XDFP-REGISTERS", which are used by the XDFP on-chip controller. Access to these registers is achieved by subaddressing. - Writing to these registers is done by sending the device write address first, followed by the XDFPwrite subaddress, two address bits for the desired XDFP-register, and the two data bytes. - For reading, the XDFP-register address has to be transmitted first by sending the device write address, followed by the XDFP-read subaddress and the two XDFP-register address bytes. Without sending a stop condition, reading of the addressed data is done by sending the device read address and reading two bytes of data. Fig. 3-3 shows I2C protocol for read and write operations. Table 3-3 gives definitions of the XDFP control and status registers. If these registers are smaller than 16 bit, the remaining bits should be 0 on write and read operations. Due to the internal architecture, the IC cannot react immediately to an I2C request, which interacts with the on-chip controller. The maximum response timing is approximately 20 ms. If the addressed controller is not ready for further transmissions on the I2C-bus, the clock line SCL is pulled low. This puts the current transmission into a wait state. After a certain period of time, the clock line will be released and the interrupted transmission is carried on. A hardware reset initializes all control registers to 0. The automatic chip initialization loads a selected set of registers with the default values given in Table 3-3.
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Table 3-1: XDFP read/write address XDFP Read address XDFP Write address
h'13 h'12
The register modes are 8/16r w r/w bit width read only register write only register write/read data register
Note: set unused bits to `0`! The mnemonics used in the DDP 3310B demo software are given in the last column.
Write to XDFP Control Register:
S 1000101 W Ack XDFP Write Addr. Ack High-Byte Addr. Ack Low-Byte Addr. Ack High-Byte data Ack Low-Byte Data Ack P
Read from XDFP Control Register:
S 1000101 W Ack XDFP Read Addr. Ack High-Byte Addr. Ack Low-Byte Addr. Ack S 1000101 R Ack High-Byte Data Ack Low-Byte Data Nak P
W = 0 (Write Bit) R = 1 (Read Bit)
S = Start Condition P = Stop Condition
Ack = 0 (Acknowledge Bit from DDP 3310B=gray or Controller = hatched) Nak = 1 (Not Acknowledge Bit from Controller=hatched or indicating an error state from DDP 3310B=gray)
Fig. 3-3: XDFP protocol
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DDP 3310B
Table 3-2: I2C Control Registers
I2C Control and Status Registers Subaddr. Mode Function XDFP INTERFACE h'13 16-w XDFP read address bit[[9:0] bit[15:10] h'12 16-w 0 10-bit XDFP RAM address reserved, set to zero DFPWR 10-bit XDFP RAM address reserved, set to zero ANALOG FAST-BLANK MONITOR h'1E 8-r Fast-Blank signal status bit[0] bit[1] bit[7:2] h'11 16-r/w 0/1 FBLIN level Low/High FBLIN slope: 1 = falling edge occurred not used PFC 0 0 0 0 PFCB PFCG PFCR FBLSTAT FBLEV FBSLO DFPRD Default Name
XDFP write address bit[[9:0] bit[15:10]
picture frame color, 12 bit wide bit[3:0] bit[7:4] bit[11:8] bit[15:12] 0..15 0..15 0..15 0 blue amplitude green amplitude red amplitude not used OUTPUT PINS
h'10
8-r/w
output pin configuration bit[2:0] pin driver strength, FIFO control 7 = output tristate 6 = minimum strength 0 = maximum strength 0/1 0/1 0/1 0/1 0/1 strong/weak driver strength PWM1 strong/weak driver strength PWM2 disable/enable internal resistor for vertical and East/West drive output High/Low-active horizontal flyback input disable/enable following I/O pin: FIFO -controll signals, PWM1&2, HCS, R/G/BIN2, and VS2. 0
PSTR PSTSY
bit[3] bit[4] bit[5] bit[6] bit[7]
0 0 0 0 0
PSTPR1 PSTPR2 VEWXR FLYPOL OSDOFF
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DDP 3310B
Table 3-3: Control Registers of the XDFP
XDFP Control and Status Registers Subaddr. Mode Function INPUT FORMATTER h'1B0 16-r/w Input format bit [0] bit [1] bit [2] bit [4:3] 0/1 0/1 0/1 0...3 4:2:2 / 4:1:1 mode binary offset / 2`s complement enable / disable blanking to black ( for luma and chroma input when HS = 0 ) select color multiplex SCALER CONTROL REGISTER h'1C1 16-r/w scaler mode register bit[1:0] scaler mode 0 linear scaling mode 1 non-linear scaling mode, 'panorama' 2 non-linear scaling mode, 'waterglass' 3 reserved reserved, set to 0 reserved, set to 0 0 0 scaler update command, set to 1 to update only scaler mode register scaler update command, set to 1 to update all scaler control registers
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Default
Name
INFMT 1 1 1 0 M411 COB BLNK CMUX
0
SCMODE PANO
bit[2] bit[13:3] bit[14] bit[15] h'1C2 16-r/w
0 0 720
SCMODUP SCUPDATE FFLIM
active video length for 1-h FIFO bit[11:0] 0...1295 720 length in pixels LLC mode (864/h)
h'1C3
16-r/w
scaler1 coefficient; this scaler compresses the signal. bit[11:0] 1024..4095 compression by a factor c, the value c*1024 is required
1024
SCINC1
h'1C4
16-r/w
scaler2 coefficient; this scaler expands the signal. bit[11:0] 256..1024 expansion by a factor c, the value 1/c*1024 is required 0...4095 scaler1/2 non-linear scaling coefficient
682
SCINC2
h'1C5 h'1C6 ... h'1CA h'1CB ... h'1CF
16-r/w 16-r/w
bit[11:0]
0 0 ... 0 0 ... 0
SCINC SCW1_1 ... SCW1_5 SCW2_1 ... SCW2_5
scaler1 window controls (see Table 3-4) bit[11:0] 0...4095 5 registers for control of the non-linear scaling
16-r/w
scaler2 window controls (see Table 3-4) bit[11:0] 0...4095 5 registers for control of the non-linear scaling
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DDP 3310B
Table 3-3: Control Registers of the XDFP, continued
XDFP Control and Status Registers Subaddr. Mode Function CHROMA CHANNEL h'1AF 16-r/w luma/chroma matching delay bit [2:0] bit [3] bit [4] bit [5] h'1AB 16-r/w 0/1 -2...2 variable chroma delay not used, set to "0" CB (U) sample first / CR (V) sample first not used, set to "0" DTICTRL 1 5 1 DTICO DTIGA DTIMO 0 0 0 ENVU CRCTRL CDEL Default Name
digital transient improvement bit [3:0] bit [7:4] bit [8] 0..15 0..15 0/1 coring value DTI gain narrow/wide bandwidth mode LUMA CHANNEL
h'1B1 h'19A h'1AA
16-r/w 16-r/w 16-r/w
bit [14:9] bit [8:0]
0..63
picture contrast in steps of 1/32
32 0
CTM BRM PK1
-256..255 luma DC-offset
luma peaking filter, the gain at high frequencies and small signal amplitudes is: 1 + (k1+k2)/8
bit [3:0] bit [7:4] bit [8] 0..15 0..15 0/1 k1: peaking level undershoot k2: peaking level overshoot peaking value normal/inverted (peaking/softening) 4 4 0
PKUN PKOV PKINV
h'1AE
16-r/w
luma peaking filter, coring bit [4:0] bit [7:5] 000 001 01x 100 101 11x bit [8] 0/1 0..31 coring level peaking reduction 100 % 80 % 60 % 50 % 40 % 30 % peaking filter center frequency High/Low 3 0
PK2 COR PKRD
0
PFS LSLS
h'18A
16-r/w
luma soft limiter, slope A and B bit [3:0] bit [7:4] slope segment A slope segment B 0 0
LSLSA LSLSB LSLA
h'18E
16-r/w
luma soft limiter, limit A bit [7:0] bit [8] 0/1 luma soft limiter absolute limit (unsigned) modulation off/on (resolution enhancement) 255 0 300 luma soft limiter segment B tilt point (unsigned) luma soft limiter segment A tilt point (unsigned) 250
LSLAL LSLM LSLTB
h'192
16-r/w
luma soft limiter, limit B bit [8:0]
h'196
16-r/w
bit [8:0]
LSLTA
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DDP 3310B
Table 3-3: Control Registers of the XDFP, continued
XDFP Control and Status Registers Subaddr. Mode Function INVERSE MATRIX h'1B9 h'1B8 16-r/w picture matrix coefficient R-Y = MR1M/64*CB + MR2M/64*CR bit [15:7] bit [15:7] h'1B7 h'1B6 16-r/w -256... 255 -256... 255
ADVANCE INFORMATION
Default
Name
0 86
MR1M MR2M
picture matrix coefficient G-Y = MG1M/64*CB + MG2M/64*CR bit [15:7] bit [15:7] -256... 255 -256... 255 -22 -44 MG1M MG2M
h'1B5 h'1B4
16-r/w
picture matrix coefficient B-Y = MB1M/64*CB + MB2M/64*CR bit [15:7] bit [15:7] -256... 255 -256... 255 0...63 -1 0...127 picture saturation in steps of 1/32; reserved mode to use old MATRIX coefficients and CTM addresses from B1 limit for picture contrast x saturation in steps of 1/32 PICTURE FRAME GENERATOR 113 0 -1 MB1M MB2M SATM
h'1B2
16-r/w
bit [15:9]
h'1B3
16-r/w
bit [14:8]
80
SATLIM
h'197
16-r/w
picture frame insertion contrast R (amplitude range:0 to 255) bit [7:4] 0..13 14,15 R amplitude = PFCR * (PFRCT + 4) invalid 8 PFRCT
h'193
16-r/w
picture frame insertion contrast G (amplitude range:0 to 255) bit [7:4] 0..13 14,15 G amplitude = PFCG * (PFGCT + 4) invalid 8 PFGCT
h'18F
16-r/w
picture frame insertion contrast B (amplitude range:0 to 255) bit [7:4] 0..13 14,15 0...1295 0 7FF B amplitude = PFCB * (PFBCT + 4) invalid horizontal picture frame begin (see Table 2-5 for max. pixels per line) horizontally disabled full frame horizontal picture frame end (see Table 2-5 for max. pixels per line) vertical picture frame start line (+128) vertically disabled vertical picture frame end line disable/enable analog FastBlank input1/2 if bit[x] is set to 1, then the function is active for the respective signal priority picture frame generator priority id enable prio id for picture frame generator 8 0 PFBCT PFGHB
h'1D5
16-r/w
bit [10:0]
h'1D6 h'1AC h'1A8 h'198
16-r/w 16-r/w 16-r/w 16-r/w
bit [10:0] bit [8:0] bit [8:0] bit [7:0]
0...1295 0...511 0 0...511 0/1:
0 0 57 0
PFGHE PFGVB PFGVE PBFB1
h'194
16-r/w
bit [2:0] bit [8]
0...7 0/1
7 1
PFGID PFGEN
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DDP 3310B
Table 3-3: Control Registers of the XDFP, continued
XDFP Control and Status Registers Subaddr. Mode Function SCAN VELOCITY MODULATION h'1A7 16-r/w video mode coefficients bit [5:0] bit [8:6] h'19F 16-r/w limiter bit [7:0] bit [8:5] h'19B 16-r/w 0...255 0 limit value not used, set to"0" 100 0 SVM2 delay of SVMOUT in steps of 12.5 ns (7 = SVMOUT vs. RGBOUT is 60ns) coring value not used, set to"0" TUBE MEASUREMENT h'19C 16-r/w tube measurement line bit [8:0] h'15F h'186 16-r/w 16-r/w bit[10:0] 0..511 0... 1295 start line for tube measurement (+2 lines) Latch timing of madc data in pixels before the begin of horiz. blanking HBST 128 384 MADCLAT WDRM 10 TML 7 0 SVDEL SVCOR SVLIM 0...63 0...6 gain differentiator delay (0= filter off) 60 1 SVM1 SVG SVD Default Name
delay and coring bit [3:0] bit [7:4] bit [8] 0...15 0...15 0
white drive measurement control bit [8:0] 0..511 0..511 RGB amplitude for white-drive beam current measurement Amplitude for cutoff measurement. It can be set to measure at higher cutoff current.
h'168
16-r/w
bit[14:6]
256
IBRM
h'171
16-r/w
measurement control word bit [8] bit [9] bit [10] bit [11] bit [12] bit [13] bit [14] 0/1 0/1 0/1 0/1 0/1 0/1 0/1 enable/disable ultra black blanking 0: all outputs blanked (video mute) 1: normal mode 78/156 kHz bandwidth for cutoff and drive measurement enable/disable white drive measurement enable/disable cutoff measurement disable/enable horizontal blanking during measurement disable/enable RSW1 Pin as input for beam current measurement 0 0 0 0 0 0 0
MCTRL ULBLK_DIS BLANK_DIS BW_SEL WDR_DIS CUT_DIS MBLANK SMODE
Micronas
27
DDP 3310B
Table 3-3: Control Registers of the XDFP, continued
XDFP Control and Status Registers Subaddr. Mode Function BRIGHTNESS and CONTRAST h'165 16-r/w bit[14:6] 0..511 analog contrast for external RGB
ADVANCE INFORMATION
Default
Name
360
EXT_CONTR
h'166 h'167
16-r/w 16-r/w
bit[15:6] -256..255 analog brightness for external RGB The range allows for both increase and reduction of brightness. bit[15:6] -256..255 internal analog brightness The range allows for both increase and reduction of brightness. BCL
128 24
EXT_BRT INT_BRT
h'D7 h'160
16-r/w 16-r/w
bit[14:3] bit[15:4]
0..4095 0... 2047 0...-2048 0...511 0...511 0...511 0...511
measured beam current, latched every line except during vertical blanking BCL threshold current if SENSE input used BCL threshold current if RSW1 input used (max. ADC output ~2047) BCL time constant; 0 = off BCL loop gain BCL minimum contrast; (= 0..max contrast) BCL minimum brightness; (= 0..max bright.)
0
BC BCL_THRES
64
h'161 h'162 h'163 h'164
16-r/w 16-r/w 16-r/w 16-r/w
bit[8:0] bit[14:6] bit[14:6] bit[14:6]
0 0 256 256
BCL_TC BCL_GAIN BCL_MIN_C BCL_MIN_B
28
Micronas
ADVANCE INFORMATION
DDP 3310B
Table 3-3: Control Registers of the XDFP, continued
XDFP Control and Status Registers Subaddr. Mode Function CUTOFF and DRIVE h'169 h'16A h'16B h'D3 h'D4 h'D5 h'16C 16-r/w 16-r/w 16-r/w 16-r 16-r 16-r 16-r/w bit[12:4] bit[12:4] bit[12:4] bit[11:4] bit[11:4] bit[11:4] bit[14:6] 0...511 0...511 0...511 0...255 0...255 0...255 0...511 0 0...511 0...511 0...511 0...255 0...255 0...255 0...511 0 reference for cutoff Red reference for cutoff Green reference for cutoff Blue measured cutoff Red measured cutoff Green measured cutoff Blue gain for cutoff control loop; the reference values are taken directly as cutoff values reference for White Drive Red reference for White Drive Green reference for White Drive Blue measured White Drive Red measured White Drive Green measured White Drive Blue gain for White Drive control loop; the reference values are taken directly as white drive values 511 511 511 0 0 0 0 CUT_R CUT_G CUT_B CUTOFF_R CUTOFF_G CUTOFF_B CUT_GAIN Default Name
h'16D h'16E h'16F h'D0 h'D1 h'D2 h'170
16-r/w 16-r/w 16-r/w 16-r 16-r 16-r 16-r/w
bit[12:4] bit[12:4] bit[12:4] bit[11:4] bit[11:4] bit[11:4] bit[14:6]
511 511 511 0 0 0 0
WDR_R WDR_G WDR_B WDRIVE_R WDRIVE_G WDRIVE_B WDR_GAIN
h'172 h'1E9
16-r/w 16-r/w
bit[14:6] bit[0]
475 ...511 threshold for automatic drive saturation avoidance 0/1 disable/enable automatic drive saturation avoidance
491 0
MAX_WDR WDR_SAT
Micronas
29
DDP 3310B
Table 3-3: Control Registers of the XDFP, continued
XDFP Control and Status Registers Subaddr. Mode Function DISPLAY FREQUENCY DOUBLING h'176 16-r/w display frequency doubling control word bit[1:0] display raster mode (A' = field A in raster B) 0 = A A` B` B 1=AA B B 2 = A A B` B` 3=not used minimum field length filter 0 = off 1 = 2 fields 2 = 3 fields 3 = 4 fields input sync doubling switch 0 = leave H and V sync unchanged 1 = double VSYNC and leave HSYNC unchanged 2 = double HSYNC and leave VSYNC unchanged 3 = double H and V sync clock switch 0 = Clock from LLC2 pin divided by 2 1 = Clock from LLC1 pin test bit, set to 0 0 1 0/1 0/1 0/1 0/1 automatic VS/VS2 polarity detection Low-active VS/VS2 input High/Low-active HS input VS / VS2 Pin is source of VSYNC dis-/enable still picture (only available if display frequency doubling is enabled) High / Low-active FIFO controll signals TIMING h'1A4 16-r/w vertical blanking start bit [8:0] h'1A0 16-r/w 0..511 first line of vertical blanking (+ 128 offset)
ADVANCE INFORMATION
Default
Name
DFDCTRL 0 DFDMODE
bit[3:2]
0
DFDFILT
bit[5:4]
0
DFDSW
bit[6]
0
DFDCLK
bit[7] bit[8] bit[9] bit[10] bit[11] bit[12]
0 0 0 0 0 0 VSYPOL HSYPOL VSYSRC STILL FIFOPOL
182
VBST
vertical blanking stop bit [8:0] 0..511 0..1295 0..1295 0..1295 last line of vertical blanking horizontal blanking start (see Table 2-5 for max. pixels per line) horizontal blanking stop (see Table 2-5 for max. pixels per line) Start at active video relative to pixel counter. (see Table 2-5 for max. pixels per line) start point of active video relative to incoming HS signal in steps of 2 LLC2 clocks; can be used e.g. for panning
22
VBSO
h'1D3 h'1D4 h'1D2
16-r/w 16-r/w 16-r/w
bit[10:0] bit[10:0] bit[10:0]
253 331 330
HBST HBSO NEWLIN
h'18b
16-r/w
bit [8:0]
0...511
0
SFIF
30
Micronas
ADVANCE INFORMATION
DDP 3310B
Table 3-3: Control Registers of the XDFP, continued
XDFP Control and Status Registers Subaddr. Mode Function HORIZONTAL DEFLECTION h'1D1 h'140 16-r/w 16-r/w bit [5:0] 20..35 horizontal drive pulse duration (High time) 30 HDRV HCTRL 0 0 0 0 0 0 VPROT_DIS HPROT_DIS EFLB RAMP_EN HFREQ Default Name
horizontal deflection control register bit [0] bit [1] bit [2] bit [3] bit [4] bit [7:5] 0 0/1 0/1 0/1 1 0..7 000 001 010 100 101 110 reserved, set to 0 enable/disable vertical protection enable/disable H-safety protection disable/enable drive high during flyback start ramp up/down horizontal frequency H-Freq. pixels per line @LLC in kHz 27 MHz 32 MHz 31.25 864 1024 35.1 768 912 31.46 858 1024 33.8 800 944 37.5 720 852 37.9 712 844
h'141
16-r/w
adjustable delay of PLL2, clamping, and blanking (relative to incoming hsync) adjust clamping pulse for analog RGB input
bit [15:1] Range 600, 1 step = 1 pixel clock
5
POFS2
h'144
16-r/w
adjustable delay of flyback, H/VSYNC and analog RGB (relative to PLL2) adjust horizontal drive or H/VSYNC
bit [15:1] Range 600, 1 step = 1 pixel clock
0
POFS3
h'145 h'142
16-r/w
PLL2/3 filter coefficients
bit [14:6] bit [14:6] 0...511 0...511 proportional coefficient PLL3, c*2^-9 proportional coefficient PLL2, c*2^-9 102 184 0 0 PKP3 PKP2 ANGLE BOW
h'14A h'14B
16-r/w 16-r/w
bit[15:6] bit[15:6]
-512...511 vertical angle -512...511 vertical bow VERTICAL MODES
h'1E2 h'1E3
16-r/w 16-r/w
bit [0] raster mode bit [1:0]
0/1
VSYNC synchronized/ free running
0 0
VS_MODE R_MODE
0 1 2 3 0/1
same input and output raster field 2 is delayed (only A raster is written) field 1 is delayed (only B raster is written) not used automatic lines-per-field adaption (constant raster amplitude) off/on 0 VA_MODE
h'1E8
16-r/w
bit [0]
Micronas
31
DDP 3310B
Table 3-3: Control Registers of the XDFP, continued
XDFP Control and Status Registers Subaddr. Mode Function VERTICAL PARAMETERS h'152 h'153 h'154 h'155 16-r/w 16-r/w 16-r/w 16-r/w bit [6:0] bit [9:0] bit [9:0] bit [9:0] 0... 127 0... 1023 0... 1023 0... 1023 window (LPFDVSYNWIN) for sync detection lines per field number of hold lines number of flyback lines (flyback booster active)
ADVANCE INFORMATION
Default
Name
32 312 10 5
VSYNWIN LPFD HOLDL FLYBL
VERTICAL SAWTOOTH CORRECTION (%-values according to DAC range) h'14D h'14E h'14F 16-r/w 16-r/w 16-r/w bit [15:8] bit [14:6] bit [15:8] -128...127 vertical amplitude (25 %) 0...510 zoom (0...100...200 %) 0 256 0 AMPL ZOOM VPOS
-128...127 vertical picture position ( 50 %) (DC offset of Sawtooth output). This offset is independent of EHT compensation. -128...127 linearity (10 %) -128...127 S-correction (8 %)
h'150 h'151
16-r/w 16-r/w
bit [15:8] bit [15:8]
0 0
LIN SCORR
EAST-WEST PARABOLA (%-values according to DAC range) h'157 h'158 h'159 h'15A h'15B 16-r/w 16-r/w 16-r/w 16-r/w 16-r/w bit [15:7] bit [15:8] bit [15:8] bit [15:8] bit [15:8] -256..255 picture width (0...100 %) -128...127 trapez correction (100 %) -128...127 cushion correction (100 %) -128...127 upper corner correction (100 %) -128...127 lower corner correction (100 %) 51 0 0 0 0 WIDTH TCORR CUSH CRNU CRNL
EXTREME HIGH-TENSION (EHT) COMPENSATION (%-values according to DAC range) h'148 h'149 16-r/w 16-r/w bit[15:6] bit[14:6] -512...511 EHT compensation coefficient for horizontal phase (1.5s) 0...511 EHT time constant for horizontal phase compensation 0 = off 0 0 EHTHP EHTH_TC
h'147 h'15C h'15D
16-r/w 16-r/w 16-r/w
bit[15:6] bit [15:6] bit [14:6]
-512...511 EHT compensation coefficient for horizontal amplitude (100 %) -512...511 EHT compensation coefficient for vertical amplitude (25 %) 0...511 time constant for control of vertical and horizontal amplitude EHT compensation 0 = off
0 0 0
EHTH EHTV EHTV_TC
32
Micronas
ADVANCE INFORMATION
DDP 3310B
Table 3-3: Control Registers of the XDFP, continued
XDFP Control and Status Registers Subaddr. Mode Function Default Name
ANALOG RGB INSERTION
h'17A 16-r/w Fast-Blank interface mode bit [0] bit [1] bit [2] bit[3] 0 1 bit [4] bit [5] bit[6] bit[7] bit[8] bit[9] bit[10] bit[11] bit[12] 0 1 0 1 0/1 0/1 0/1 0/1 0 1 0 1 0 1 0 1 0/1 0 1 Fast-Blank from FBLIN1 pin force internal Fast-Blank signal to High Fast-Blank active High/Low at FBLIN pin Fast-Blank from FBLIN1 pin force internal Fast-Blank signal to Low Fast-Blank priority FBLIN1>FBLIN2 FBLIN10 0 0 0 0 0 0 0 0
FBFOL2 FBFOH2 FBMON CLAMP HCSPOL HCSEN HCSFOH C1_B C2_B
I2C-CONTROLLED 8-BIT PWM
h'178 h'179 16-r/w 16-r/w bit[7:0] bit[7:0] 0..255 0..255 PWM1 data word PWM2 data word 0 0 PWM1 PWM2
XDFP STATUS REGISTER
h'0 16-r/w firmware version number bit[7:0] bit[15:8] firmware release hardware version number (TC) - - VER FW_REL HW_VER
Micronas
33
DDP 3310B
3.3.1. Scaler Adjustment In case of linear scaling, most of the scaler registers need not be set. Only the scaler mode, active video length, and the fixed scaler increments (SCINC1 / SCINC2) must be written. For adjustment of the scaler for non-linear scaling, the parameters given in Table 3-4 should be used. An example for "panorama vision" mode is depicted in Border Compression Ratio Zoom 1 Compression
ADVANCE INFORMATION
Fig. 3-4. It shows the scaling of the input signal and the variation of the scaling factor during the active video line. The scaling factor starts below 1, i.e. for the borders the video data is expanded and after it exceeds 1 it is compressed. When the picture center is reached, the scaling factor is kept constant. At the second border the scaling factor changes back symmetrically.
Center
Border
Zoom t
Input Signal
Output Signal Fig. 3-4: Scaler operation for "panorama" mode Table 3-4: Setup values for non-linear scaler modes
Mode `waterglass' border 35 % Register SCINC1 SCINC2 SCINC FFLIM SCW1 - 0 SCW1 - 1 SCW1 - 2 SCW1 - 3 SCW1 - 4 SCW2 - 0 SCW2 - 1 SCW2 - 2 SCW2 - 3 SCW2 - 4 center 3/4 1099 1024 60 715 20 156 202 338 358 20 156 384 520 540 center 5/6 1064 1024 65 717 10 123 236 349 359 10 123 417 530 540 27 MHz `panorama' border 30 % center 4/3 1024 259 56 758 106 106 273 273 379 186 186 354 354 540 center 6/5 1024 407 38 796 106 106 292 292 398 177 177 363 363 540 `waterglass' border 35 % center 3/4 1195 1024 54 833 51 161 256 366 417 51 161 373 483 534 center 5/6 1122 1024 42 845 37 166 257 386 423 37 166 368 497 534 32 MHz `panorama' border 30 % center 4/3 1024 305 68 831 109 125 291 307 416 168 184 350 366 534 center 6/5 1024 489 46 871 126 126 310 310 436 175 175 359 359 534
34
Micronas
ADVANCE INFORMATION
DDP 3310B
4. Specifications 4.1. Outline Dimensions
1.2 x 45 9 10 1 61 0.46 60 1.0 16 x 1.27 = 20.32 1.27 1.1 x 45
1.27 26 27 25.14 4.4 43 44 1.7 3.8 0.1 24.2
SPGS0027-2(K)/1E
Fig. 4-1: 68-Pin Plastic Leaded Chip Carrier with heat spreader (PLCC68K) Weight approximately 4.8 g Dimensions in mm
4.2. Pin Connections and Short Descriptions NC = not connected LV = if not used, leave vacant X = obligatory; connect as described in circuit diagram Pin No.
PLCCK 68-pin
0.23
IN = Input OUT = Output SUPPLY = Supply Pin Short Description
Pin Name
Type
Connection
(If not used)
1 2 3 4 5 6 7 8 9 10 11
VSUPP GNDP VS2 FIFORRD FIFORD FIFOWR FIFORWR HOUT HFLB SAFETY VPROT
SUPPLY SUPPLY IN OUT OUT OUT OUT OUT IN IN IN
X X GNDD LV LV LV LV X HOUT GNDO GNDO
Supply Voltage, Output Pin Driver Ground, Output Pin Driver Additional VSYNC input FIFO Read counter Reset FIFO Read Enable FIFO Write Enable FIFO Write counter Reset Horizontal Drive Output Horizontal Flyback Input Safety Input Vertical Protection Input
Micronas
16 x 1.27 = 20.32
0.74
25.14
23.1
24.2
35
DDP 3310B
ADVANCE INFORMATION
Pin No.
PLCCK 68-pin
Pin Name
Type
Connection
(If not used)
Short Description
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
FREQSEL CM1 CM0 RSW2 RSW1 SENSE GNDM VERT+ VERT- EW XREF SVM ROUT GOUT BOUT GNDO VSUPO VRD/BCS FBLIN1 RIN1 GIN1 BIN1 FBLIN2 RIN2 GIN2 BIN2 TEST RESQ PWM1 PWM2 HCS
IN IN IN OUT IN/OUT IN SUPPLY OUT OUT OUT IN OUT OUT OUT OUT SUPPLY SUPPLY IN IN IN IN IN IN IN IN IN IN IN OUT OUT IN
X X X LV LV GNDO X GNDO GNDO GNDO X VSUPO VSUPO VSUPO VSUPO X X X GNDO GNDO GNDO GNDO GNDO GNDO GNDO GNDO GNDD X LV LV GNDD
Selection of H-Drive Frequency Range Clock Select 40.5 or 27/32 MHz Clock select 27/32 MHz Range Switch2, Measurement ADC Range Switch1, Measurement ADC Sense ADC Input Ground, MADC Input Differential Vertical Sawtooth Output Differential Vertical Sawtooth Output Vertical Parabola Output Reference Input for RGB DACs Scan Velocity Modulation Analog Output Red Analog Output Green Analog Output Blue Ground, Analog Back-end Supply Voltage, Analog Back-end DAC Reference, Beam Current Safety Fast-Blank1 Input Analog Red1 Input Analog Green1 Input Analog Blue1 Input Fast-Blank2 Input Analog Red2 Input Analog Green2 Input Analog Blue2 Input Test Pin Reset Input, active low I2C-controlled DAC I2C-controlled DAC Half-Contrast
36
Micronas
ADVANCE INFORMATION
DDP 3310B
Pin No.
PLCCK 68-pin
Pin Name
Type
Connection
(If not used)
Short Description
43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
C0 C1 C2 C3 C4 C5 C6 C7 VSUPD GNDD LLC2 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 LLC1 HS VS XTAL2 XTAL1 SDA SCL
IN IN IN IN IN IN IN IN SUPPLY SUPPLY IN IN IN IN IN IN IN IN IN IN IN IN OUT IN IN/OUT IN/OUT
GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD X X X GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD VSUPD X GNDD X X X X
Picture Bus Chroma (LSB) Picture Bus Chroma Picture Bus Chroma Picture Bus Chroma Picture Bus Chroma Picture Bus Chroma Picture Bus Chroma Picture Bus Chroma (MSB) Supply Voltage, Digital Circuitry Ground, Digital Circuitry System Clock Input (27/32/40.5 MHz) Picture Bus Luma (LSB) Picture Bus Luma Picture Bus Luma Picture Bus Luma Picture Bus Luma Picture Bus Luma Picture Bus Luma Picture Bus Luma (MSB) Single Line-Locked Clock Input (13.5/16 MHz) Horizontal Sync Input Vertical Sync Input Analog Crystal Output (5-MHz Security Clock) Analog Crystal Input (5-MHz Security Clock) I2C-Bus Data I2C-Bus Clock
Micronas
37
DDP 3310B
4.3. Pin Description Pin 1 - Supply Voltage, Output Pin Driver VSUPP* This pin is used as supply for the following digital output pins: FIFORRD, FIFORD, FIFOWR, FIFORWR. Pin 2 - Ground, Output Pin Driver GNDP* Output Pin Driver Reference Pin 3 - Sync Signal Input VS2 (Fig. 4-3) Additional pin for the vertical sync information. Via I2CRegister the used vertical sync can be switched between the inputs VS2 and VS (Pin 64) Pin 4 - Reset for FIFO Read Counter FIFORRD (Fig. 4-4) This signal is active-High and resets the read counter in the display frequency doubling FIFO. Pin 5 - Read Enable for FIFO FIFORD (Fig. 4-4) This signal is active-High and enables the read counter in the display frequency doubling FIFO. Pin 6 - Write Enable for FIFO FIFOWR (Fig. 4-4) This signal is active-High and enables the write counter in the display frequency doubling FIFO. Pin 7 - Reset for FIFO Write Counter FIFORWR (Fig. 4-4) This signal is active-High and resets the write counter in the display frequency doubling FIFO. Pin 8 - Horizontal Drive HOUT (Fig. 4-5) This open-drain output supplies the drive pulse for the horizontal output stage. A pull-up resistor has to be used (see Section 2.3.). Pin 9 - Horizontal Flyback Input HFLB (Fig. 4-6) Via this pin, the horizontal flyback pulse is supplied to the DDP 3310B (see Section 2.3.). Pin 10 - Safety Input SAFETY (Fig. 4-6) This input has two thresholds. A signal between the lower and upper threshold means normal function. Other signals are detected as malfunction (see Section 2.3.9.). Pin 11 - Vertical Protection Input VPROT (Fig. 4-7) The vertical protection circuitry prevents the picture tube from burn-in in the event of a malfunction of the vertical deflection stage. If the peak-to-peak value of the vertical sawtooth signal is too small, the RGB output signals are blanked (see Section 2.3.9.). Pin 12 - H-Drive Frequency Range Select FREQSEL (Fig. 4-3) This pin selects the frequency range for the horizontal drive signal (see Section 2.3.2.).
ADVANCE INFORMATION
Pin 13 - Clock Select 40.5 or 27/32 MHz CM1 (Fig. 4-3) Low level selects 27/32 MHz, High level selects 40.5 MHz (see Section 2.3.12.). Pin 14 - Clock Select 27 or 32 MHz CM0 (Fig. 4-3) Low level selects 27 MHz, High level selects 32 MHz (see Section 2.3.12.). Pin 15 - Range Switch2 for Measuring ADC RSW2 (Fig. 4-8) This pin is an open-drain pull-down output. During cutoff measurement the switch is off. During white drive measurement the switch is on. Also during the rest of time it is on. (see Section 2.2.4.). Pin 16 - Range Switch1 or Second Input for Measuring ADC RSW1 (Fig. 4-9) This pin is an open-drain pull-down output. During cutoff and white-drive measurement, the switch is off. During the rest of time it is on. The RSW1 pin can be used as second measurement ADC input (see Section 2.2.4.). Pin 17 - Measurement ADC Input SENSE (Fig. 4-10) This is the input of the analog to digital converter for the picture and tube measurement. Three measurement ranges are selectable with RSW1 and RSW2 (see Section 2.2.4.). Pin 18 - Measurement ADC Reference Input MGND This is the ground reference for the measurement A/D converter. Pin 19 - Vertical Sawtooth Output VERT+ (19) (Fig. 4-11) This pin supplies the drive signal for the vertical output stage. The drive signal is generated with 15-bit precision. The analog voltage is generated by a 4-bit current DAC with external resistor (6 k for proper operation) and uses digital noise-shaping. Pin 20 - Vertical Sawtooth Output inverted VERT- (Fig. 4-11) This pin supplies the inverted signal of VERT+. Together with this pin, it can be used to drive symmetrical deflection amplifiers. Pin 21 - East/West Parabola Output EW (Fig. 4-12) This pin supplies the parabola signal for the East/West correction. The drive signal is generated with 15-bit precision. The analog voltage is generated by a 4-bit current DAC with external resistor and uses digital noise-shaping.
38
Micronas
ADVANCE INFORMATION
DDP 3310B
Pin 35, 36, 37 - Analog RGB Input2 RIN2, GIN2, BIN2 (Fig. 4-15) These pins are used to insert an external analog RGB signal, e.g. from a SCART connector which can by switched to the analog RGB outputs with the FastBlank signal. The analog back-end provides separate brightness and contrast settings for the external analog RGB signals (see Section 2.2.1. and Fig. ). Pin 38 - Test Input TEST (Fig. 4-16) This pin enables factory test modes. For normal operation it must be connected to ground. Pin 39 - Reset Input RESQ (Fig. 4-16) A low level on this pin resets the DDP 3310B. Pin 40 - Adjustable DC Output 1 PWM1 (Fig. 4-17) This output delivers a DC voltage with a resolution of 8 bit, adjustable over the I2C bus. The output is driven by a push-pull stage. The PWM frequency is appr. 79.4 kHz. For a ripple-free voltage a first order lowpass filter with a corner frequency <120 Hz should be applied. Pin 41 - Adjustable DC Output 2 PWM2 (Fig. 4-17) See pin 40. Pin 42 - Half-Contrast Input HCS (Fig. 4-18) Via this input pin the output level of the D/A-converted internal RGB signals can be reduced by 6 dB. Inserted external analog RGB signals remain unchanged. Pin 43...50 - Picture Bus Chroma C0...C7 (Fig. 4-3) The Picture Bus Chroma lines carry the multiplexed color component data. For the 4:1:1 input signal (4-bit chroma) the pins C4...C7 are used. Pin 51 - Supply Voltage, Digital Circuitry VSUPD* Pin 52 - Ground, Digital Circuitry GNDD* Digital Circuitry Input Reference Pin 53 - Main Clock Input LLC2 (53) (Fig. 4-16) This is the input for the line-locked clock signal. The frequency can be 27, 32, or 40.5 MHz. Pin 54...61 - Picture Bus Luma Y0...Y7 (Fig. 4-3) The Picture Bus Luma lines carry the digital luminance data. Pin 62 - Line-Locked Clock Input LLC1 (Fig. 4-16) This is the reference clock for the single frequency input sync signals required in a FIFO application. The frequency can be 13.5, 16, or 20.25 MHz.
Pin 22 - DAC Current Reference XREF (Fig. 4-13) External reference resistor for DAC output currents, typical 10 k, to adjust the output current of the D/A converters. (see recommended operating conditions). This resistor has to be connected to analog ground as closely as possible to the pin. Pin 23 - Scan Velocity Modulation Output SVM (Fig. 4-14) This output delivers the analog SVM signal (see Section 2.1.11.). The D/A converter is a current sink like the RGB D/A converters. At zero signal the output current is 50 % of the maximum output current. Pin 24, 25, 26 - Analog RGB Output ROUT, GOUT, BOUT (Fig. 4-14) These pins are the analog Red/Green/Blue outputs of the back-end. The outputs are current sinks. Pin 27 - Ground, Analog Back-end GNDO* This pin has to be connected to the analog ground. No supply current for the digital stages should flow through this line. Pin 28 - Supply Voltage, Analog Back-end VSUPO* This pin has to be connected to the analog supply voltage. No supply current for the digital stages should flow through this line. Pin 29 - DAC Reference Decoupling/Beam Current Safety VRD/BCS (Fig. 4-13) Via this pin, the DAC reference voltage is decoupled by an external capacitor. The DAC output currents depend on this voltage, therefore a pull-down transistor can be used to shut off all beam currents. A decoupling capacitor of 4.7 F in parallel to 100 nF (low inductance) is required. Pin 30, 34 - Fast-Blank Input FBLIN1/2 (Fig. 4-7) These pins are used to switch the RGB outputs to the external analog RGB inputs. FBLIN1 switches the RIN1, GIN1 and BIN1 inputs, FBLIN2 switches the RIN2, GIN2 and BIN2 inputs. The active level (Low or High) can be selected by software. Pin 31, 32, 33 - Analog RGB Input1 RIN1, GIN1, BIN1 (Fig. 4-15) These pins are used to insert an external analog RGB signal, e.g. from a SCART connector which can by switched to the analog RGB outputs with the FastBlank signal. The analog back-end provides separate brightness and contrast settings for the external analog RGB signals (see Section 2.2.1. and Fig. ).
Micronas
39
DDP 3310B
Pin 63 - Sync Signal Input HS (Fig. 4-3) This pin gets the horizontal sync information. Either single or double horizontal frequency or VGA horizontal sync signal. Pin 64 - Sync Signal Input VS (Fig. 4-3) This pin gets the vertical sync information. Either single or double vertical frequency or VGA vertical sync signal. Pin 65, 66 - Crystal Output / Input XTAL2 / XTAL1 (Fig. 4-19) These pins are connected to an 5-MHz crystal oscillator. The security unit for the HOUT signal uses this clock signal as reference. Pin 67 - I2C Data Input/Output SDA (Fig. 4-20) Via this pin the I2C-bus data are written to or read from the DDP 3310B. Pin 68 - I2C Clock Input SCL (Fig. 4-20) Via this pin, the clock signal for the I2C-bus will be supplied. The signal can be pulled down by an internal transistor.
ADVANCE INFORMATION
* Application Note: All ground pins should be connected separately with short and low-resistive lines to a central power supply ground. Accordingly, all supply pins should be connected separately with short and low-resistive lines to the power supply. Decoupling capacitors from VSUPP to GNDP, VSUPD to GNDD, and VSUPO to GNDO are recommended to be placed as closely as possible to the pins.
40
Micronas
ADVANCE INFORMATION
DDP 3310B
4.4. Pin Configuration
VSUPP GNDP VS2 FIFORRD FIFORD FIFOWR FIFORWR HOUT HFLB SCL SDA XTAL1 XTAL2 VS HS LLC1 Y7
9 SAFETY VPROT FREQSEL CM1 CM0 RSW2 RSW1 SENSE GNDM VERT+ VERT- EW XREF SVM ROUT GOUT BOUT 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 Y6 Y5 Y4 Y3 Y2 Y1 Y0 LLC2 GNDD VSUPD C7 C6 C5 C4 C3 C2 C1
DDP 3310B
52 51 50 49 48 47 46 45 44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 GNDO VSUPO VRD/BCS FBLIN1 RIN1 GIN1 BIN1 FBLIN2 RIN2 C0 HCS PWM2 PWM1 RESQ TEST BIN2 GIN2
Fig. 4-2: 68-pin PLCCK package
Micronas
41
DDP 3310B
4.5. Pin Circuits
ADVANCE INFORMATION
VSUPD P N GNDO N GNDD Fig. 4-3: Input pins 3, 12, 13, 14, 43 to 50, 54 to 61, 63, and 64 (VS2, FREQSEL, CM1, CM0, C[7:0], Y[7:0], HS, VS) Fig. 4-8: Output pin 15 (RSW2)
P
to ADC
N N VSUPO
VSUPP P
Fig. 4-9: Input/Output pin 16 (RSW1) N GNDP Fig. 4-4: Output pins 4 to 7 (FIFORRD, FIFORD, FIFOWR, FIFORWR) P N Fig. 4-10: Input pin 17 (SENSE)
N GNDP Fig. 4-5: Output pin 8 (HOUT) P P P
VSUPO
Flyback
+
VEWXR
N
N
N GNDO
VREF Fig. 4-6: Input pins 9 to 11 (HFLB, SAFETY, VPROT)
Fig. 4-11: Output pins 19 and 20 (VERT+, VERT-)
VREF Fig. 4-7: Input pins 30 and 34 (FBLIN1, FBLIN2)
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ADVANCE INFORMATION
DDP 3310B
VSUPO
VSUPD P
P
P N
VEWXR
N GNDO
GNDD Fig. 4-17: Output pins 40 and 41 (PWM1, PWM2)
Fig. 4-12: Output pin 21 (EW) VSUPO VSUPO VRD/BCS + int. ref. voltage ref. current XREF GNDO Fig. 4-13: Input pins 22 and 29 (XREF, VDR/BCS) VSUPD N
XTAL1
P
N GNDO Fig. 4-18: Input pin 42 (HCS)
P
XTAL2
N
Bias
N GNDO
N P GNDD Fig. 4-19: Input pin 66 (XTAL1), Output pin 65 (XTAL2)
Fig. 4-14: Output pins 23 to 26 (SVM, ROUT, GOUT, BOUT)
N
Clamping
N GNDO
N GNDD Fig. 4-20: Input/Output pins 67 and 68 (SDA, SCL)
Fig. 4-15: Input pins 31 to 33 and 35 to 37 (R/G/BIN1, R/G/BIN2)
Fig. 4-16: Input pins 38, 39, 53, and 62 (TEST, RESQ, LLC2, LLC1)
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DDP 3310B
4.6. Electrical Characteristics 4.6.1. Absolute Maximum Ratings
Symbol TA TC TS VSUP VI VO Parameter Ambient Operating Temperature Case Temperature Storage Temperature Supply Voltage Input Voltage Output Voltage Pin Name - - - All Supply Pins All Inputs All Outputs (except HOUT) All Ground Pins Min. 0 0 -40 -0.3 -0.3 -0.3
ADVANCE INFORMATION
Max. 65 105 125 6 VSUP(P/D/O)+0.3 VSUP(P/D/O)+0.3
Unit C C C V V V
VGD
Voltage between different ground pins
-
0.3
V
Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions/Characteristics" of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
4.6.2. Recommended Operating Conditions
Symbol TA VSUP VSUPP fsys Rxref Parameter Ambient Operating Temperature Supply Voltages, all Supply Pins (except output pin driver supply) Output Pin Driver Supply Voltage Clock Frequency RGB - DAC Current Defining Resistor VSUPP LLC2 XREF Pin Name Min. 0 4.75 3.0 25.1 9.5 Typ. - 5.0 5.0 - 10 Max. 65 5.25 5.25 43.3 10.5 Unit C V V MHz k
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ADVANCE INFORMATION
DDP 3310B
4.6.3. Recommended Crystal Characteristics
Symbol fP RR C0 CLext
see Remarks!
Parameter Parallel Resonance Frequency @ CL=16 pF Series Resonance Resistance @ CL=16 pF, fP=5 MHz Shunt (Parallel) Capacitance External Load Capacitances (from both crystal pins connected to GNDD)
Pin Name XTAL1 XTAL2
Min. -
Typ. 5
Max. -
Unit MHz
- - -
- - 27
150 6 -
pF pF
Remarks:
External capacitors at each crystal pin to ground are required. They are necessary to tune the effective load capacitance (including the capacitance of the printed circuit board and the IC package) to the required load capacitance CL of the crystal. A higher capacitance will result in a lower clock frequency. The exact value of the matching capacitor should be determined in the actual application (PCB layout). CLext = 2 (CL - CPCB - CPACK)
4.6.4. Characteristics Min./Max. values at: TA = 0 to 65 C, VSUP(P/D/O) = 4.75 to 5.25 V, Rxref = 10 k, f = 27 MHz Typical values at: TC = 70 C, VSUP(P/D/O) = 5 V, Rxref = 10 k, f = 27 MHz 4.6.4.1. General Characteristics
Symbol IVSUPO IVSUPD IVSUPP PTOT IL Parameter Current Consumption Analog Back-end Current Consumption Digital Processing Current Consumption Output Pin Driver Total Power Dissipation Input and Output Leakage Current (if not otherwise specified) Pin Name VSUPO VSUPD VSUPP Min. - - - - - Typ. 65 225 10 1.5 - Max. - - - - 0.1 Unit mA mA mA W A
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DDP 3310B
4.6.4.2. Line-locked Clock Inputs: LLC1, LLC2 (see Fig. 4-21)
Symbol VIL VIH tSK tR, tF CIN 1/TLLC1 tWL1 tWH1 1/TLLC2 tWL2 tWH2 Parameter Input Low Voltage Input High Voltage Clock skew Clock Rise / Fall Time Input Capacitance Clock Frequency Clock Low Time Clock High Time Clock Frequency Clock Low Time Clock High Time LLC2 LLC1 Pin Name LLC1 LLC2 Min. - 2.0 - - - 12.0 26 26 25.1 7 7 Typ. - - - - 5 - - - - - - 43.3 - - Max. 0.8 - 6 5 - 17.2 - Unit V V ns ns pF
ADVANCE INFORMATION
Test Conditions
MHz ns ns MHz ns ns
4.6.4.3. Luma, Chroma Inputs (see Fig. 4-21)
Symbol VIL VIH tIS tIH CIN Parameter Input Low Voltage Input High Voltage Input Setup Time Input Hold Time Input Capacitance Pin Name Y[0...7] C[0...7] Min. - 2.0 7 6 - Typ. - - - - 5 Max. 0.8 - - - - Unit V V ns ns pF Test Conditions
TLLC1 tWH1 LLC1 tR1 TLLC2 tWH2 LLC2 tR2 tF2 tIS Y,C Inputs tIH VIH VIL tWL2 VIH VIL tSK tF1 tSK tWL1 VIH VIL
Fig. 4-21: Line-locked clock input pins and luma/chroma bus input timing
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Micronas
ADVANCE INFORMATION
DDP 3310B
4.6.4.4. Reset Input, Test Input
Symbol VIL VIH CIN Parameter Input Low Voltage Input High Voltage Input Capacitance Pin Name RESQ TEST Min. - 3.2 - Typ. - - 5 Max. 2.0 - - Unit V V pF Test Conditions
4.6.4.5. Half-Contrast Input
Symbol VIL VIH CIN Parameter Input Low Voltage Input High Voltage Input Capacitance Pin Name HCS Min. - 2.0 - Typ. - - 5 Max. 0.8 - - Unit V V pF Test Conditions
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DDP 3310B
4.6.4.6. I2C-Bus Interface
Symbol VIL VIH VOL IOL CIN tF tR fSCL tLOW tHIGH tIS tIH tOS tOH Parameter Input Low Voltage Input High Voltage Output Low Voltage Output Low Current Input Capacitance Signal Fall Time Signal Rise Time Clock Frequency Low Period of SCL High Period of SCL Input Data Set Up Time to SCL high Input Data Hold Time to SCL Low Output Data Set Up Time to SCL High Output Data Hold Time to SCL Low SDA SCL Pin Name SDA SCL Min. - 3.0 - - - - - 0 1.3 0.6 55 55 100 15 Typ. - - - - - - - - - - - - - - - 900 Max. 1.5 - 0.6 10 5 300 300 400 - - - Unit V V V mA pF ns ns kHz s s ns ns ns ns
ADVANCE INFORMATION
Test Conditions
IOL = 6 mA
CL = 400 pF CL = 400 pF
1/fSCL tHIGH SCL tR tIS SDA as input tOS SDA as output tOH VIH VIL tF tIS VIH VIL tLOW VIH VIL
Fig. 4-22: I2C bus timing
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ADVANCE INFORMATION
DDP 3310B
4.6.4.7. Horizontal and Vertical Sync Inputs and Clock and Freqency Select Pins
Symbol VIL VIH CIN tIS tIH Parameter Input Low Voltage Input High Voltage Input Capacitance Input Setup Time Input Hold Time Pin Name HS VS VS2 CM0 CM1 FREQSEL HS VS VS2 Min. - 2.0 - 6 7 Typ. - - 5 - - Max. 0.8 - - - - Unit V V pF ns ns Test Conditions
VIH LLC1 tIH tIS HS, VS, VS2 Inputs VIH VIL VIL
Fig. 4-23: Sync Inputs referenced to line-locked clock
4.6.4.8. Horizontal Flyback Input
Symbol VIL VIH VIHST Parameter Input Low Voltage Input High Voltage Input Hysteresis Pin Name HFLB Min. - 2.6 0.1 Typ. - - - Max. 1.8 - - Unit V V V Test Conditions
4.6.4.9. FIFO Control Signals
Symbol VOL Parameter Output Low Voltage Pin Name FIFORRD FIFORD VOH Output High Voltage FIFORWR FIFOWR Output Transition Time VSUPP - 0.4 - - VSUPP V Min. - Typ. - Max. 0.4 Unit V Test Conditions IOL = 1.6 mA I2C[PSTSY] = 6 -IOL = 1.6 mA I2C[PSTSY] = 6 10 20 ns CLOAD = 30pF I2C[PSTSY] = 6 IOL Output Current -10 - 10 mA
tOT
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DDP 3310B
4.6.4.10. PWM Outputs
Symbol VOL Parameter Output Low Voltage Pin Name PWM1 PWM2 VOH Output High Voltage VSUPD - 0.4 - - VSUPD V Min. - Typ. - Max. 0.4 Unit V
ADVANCE INFORMATION
Test Conditions IOL = 1.6 mA I2C[PSTPR1/2] = 0 -IOL = 1.6 mA I2C[PSTPR1/2] = 0
tOT
Output Transition Time
-
20
ns
CLOAD = 10 pF Rlp = 4.7 k Clp = 100 nF I2C[PSTPR1/2] = 0
4.6.4.11. Horizontal Drive Output
Symbol VOL VOH tOF IOL Parameter Output Low Voltage Output High Voltage (Open-Drain Stage) Output Fall Time Output Low Current Pin Name HOUT Min. - - - - Typ. - - 8 - Max. 0.4 8 20 10 Unit V V ns mA Test Conditions IOL = 10 mA external pull-up resistor CLOAD = 30 pF
4.6.4.12. Vertical Protection Input (see Section 2.3.9.)
Symbol VIA VIB VIHST Parameter Input Threshold A Input Threshold B Input Hysteresis A and B Pin Name VPROT Min. 1.2 1.7 0.1 Typ. 1.0 1.5 - Max. 0.8 1.3 - Unit V V V Test Conditions
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Micronas
ADVANCE INFORMATION
DDP 3310B
4.6.4.13. Horizontal Safety Input (see Section 2.3.9.)
Symbol VIA VIB VIHST Parameter Input Threshold A Input Threshold B Input Hysteresis A and B Pin Name SAFETY Min. 2.5 3.8 0.1 Typ. 2.2 3.5 - Max. 1.9 3.2 - Unit V V V Test Conditions
4.6.4.14. Vertical and East/West D/A Converter Output
Symbol Parameter Resolution VOMIN VOMAX IDACN PSRR Minimum Output Voltage Maximum Output Voltage Full scale DAC Output Current Power Supply Rejection Ratio Pin Name EW VERT+ VERT- Min. - - 2.82 415 - Typ. 15 0 3 440 20 Max. - - 3.2 465 - Unit bit V V A dB Rload = 6.8 k Rxref = 10 k Rload = 6.8 k Rxref = 10 k Rxref = 10 k Test Conditions
4.6.4.15. Sense A/D Converter Input
Symbol VI255 C0 RI Parameter Input Voltage for code 255 Digital Output for zero Input Input Impedance Pin Name SENSE RSW1 Min. 1.4 - 1 Typ. 1.54 - - Max. 1.7 16 - Unit V LSB M Test Conditions
Range Switch Outputs RON IMax ILEAK Output On Resistance Maximum Current Leakage Current RSW1 RSW2 - - - - - - 50 15 600 mA nA RSW High Impedance IOL = 10 mA
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DDP 3310B
4.6.4.16. Analog RGB and Fast-Blank Inputs
Symbol VRGBIN VRGBIN VRGBIN Parameter External RGB Input Voltage Range Nominal RGB Input Voltage Peak-to-Peak RGB Input Voltage for Maximum Output Current Pin Name RIN1 GIN1 BIN1 RIN2 GIN2 BIN2 Min. -0.3 0.5 - - - CRGBIN External RGB Input Coupling Capacitor Clamp Pulse Width CIN IIL VCLIP VCLAMP VINOFF VINOFF RCLAMP VFBLOFF VFBLON VFBLTRIG tPID Input Capacitance Input Leakage Current RGB Input Voltage for Clipping Current Clamp Level at Input Offset Level at Input Offset Level Match at Input Clamping-ON-Resistance FBLIN Low Level FBLIN High Level Fast-Blanking Trigger Level typical Delay Fast Blanking to RGBOUT from midst of FBLIN-transition to 90% of RGBOUT- transition FBLIN1 FBLIN2 - 1.6 - -0.5 - 40 -10 -10 - - 0.9 - - Typ. - 0.7 0.44 0.7 1.1 10 - - - 2 60 - - 140 - - 0.7 8 Max. 1.1 1.0 - - - - - 13 0.5 - 80 10 10 - 0.5 - - 15 ns nF s pF A V mV mV mV V V Unit V VPP
ADVANCE INFORMATION
Test Conditions
SCART Spec: 0.7 V 3 dB Contrast setting: 511 Contrast setting: 323 Contrast setting: 204
Clamping OFF, VIN = -0.3...3 V
Clamping ON Extrapolated from VIN = 100 and 200 mV Extrapolated from VIN = 100 and 200 mV
Internal RGB = 3.75 mA (Full Scale) Internal Brightness = 0 External Brightness = 1.5 mA (Full Scale) RGBin = 0 VFBLOFF = 0.4 V VFBLON = 1.0 V Rise and fall time = 2 ns
Difference of Internal Delay to External RGBin Delay Switch-Over-Glitch
-5 -
- 0.5
+5 -
ns pAs Switch from 3.75 mA (int.) to 1.5 mA (ext.)
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Micronas
ADVANCE INFORMATION
DDP 3310B
4.6.4.17. Analog RGB Outputs, D/A Converters
Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions
Internal RGB Signal D/A Converter Characteristics Resolution IOUT IOUT IOUT IOUT IOUT IOUT IOUT IOUT Full Scale Output Current Differential Non-Linearity Integral Non-Linearity Glitch Pulse Charge Rise and Fall Time Intermodulation Signal to Noise Matching R-G, R-B, G-B R/B/G Crosstalk one channel talks two channels talk RGB Input Crosstalk from external RGB one channel talks two channels talk three channels talk Internal RGB Brightness D/A Converter Characteristics Resolution IBR IBR IBR IBR IBR IBR Full Scale Output Current relative Full Scale Output Current absolute Differential Non-Linearity Integral Non-Linearity Match R-G, R-B, G-B Match to digital RGB R-R, G-G, B-B ROUT GOUT BOUT - 39.2 - - - -2 -2 9 40 1.5 - - - - - 40.8 - 1 2 2 2 bit % mA LSB LSB % % Ref to max. digital RGB ROUT GOUT BOUT - 3.6 - - - - - +50 -2 - 10 3.75 - - 0.5 3 - - - - - 3.9 1 2 - - -50 - 2 -46 bit mA LSB LSB pAs ns dB dB % dB Passive channel: IOUT =1.88 mA Crosstalk-Signal: 1.25 MHz, 3.75 mAPP - - - - - - -50 -50 -50 dB dB dB Ramp signal, 25 output termination 10 % to 90 %, 90 % to 10 % 2/2.5 MHz full scale Signal: 1MHz full scale Bandwidth: 10MHz Rref = 10 k
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DDP 3310B
ADVANCE INFORMATION
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
RGB Output Cutoff D/A Converter Characteristics Resolution ICUT Full Scale Output Current relative Full Scale Output Current absolute Differential Non-Linearity Integral Non-Linearity Matching to digital RGB R-R, G-G, B-B RGB Output Ultrablack D/A Converter Characteristics Resolution IUB Full Scale Output Current relative Full Scale Output Current absolute ROUT GOUT BOUT - 19.6 - 1 20 0.75 - 20.4 - bit % mA Ref to max. digital RGB ROUT GOUT BOUT - 58.8 - - - -2 9 60 2.25 - - - - 61.2 - 1 2 2 bit % mA LSB LSB % Ref to max. digital RGB
External RGB Voltage/Current Converter Characteristics Resolution IEXOUT Full Scale Output Current relative Full Scale Output Current absolute CR Contrast Adjust Range Gain Match R-G, R-B, G-B ROUT GOUT BOUT - 96 9 100 - 104 bit % Ref. to max. Digital RGB VIN = 0.7 VPP, contrast = 323 Same as Digital RGB
- - -2
3.75 16:511 -
- - 2
mA
%
Measured at RGB Outputs VIN = 0.7 V, contrast = 323 Measured at RGB Outputs VIN = 0.7 V, contrast = 323 Passive channel: VIN = 0.7 V, contrast = 323 Crosstalk signal: 1.25 MHz, 3.75 mAPP
Gain Match to RGB-DACs R-R, G-G, B-B R/B/G Input Crosstalk one channel talks two channels talk RGB Input Crosstalk from Internal RGB one channel talks two channels talk tree channels talk
-3
-
3
%
-
-
-46
dB
-
-
-50
dB
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Micronas
ADVANCE INFORMATION
DDP 3310B
Symbol
Parameter RGB Input Noise and Distortion RGB Input Bandwidth -3 dB RGB Input THD
Pin Name ROUT GOUT BOUT
Min. -
Typ. -
Max. -50
Unit dB
Test Conditions VIN=0.7 VPP at 1 MHz contrast = 323 Bandwidth: 10 MHz VIN = 0.7 VPP, contrast =323 Input signal 1 MHz Input signal 6 MHz VIN = 0.7 VPP contrast =323 VIN = 0.44V
15 - - -50 -40
- - -
MHz dB dB
Differential Non-Linearity of Contrast Adjust Integral Non-Linearity of Contrast Adjust VRGBO R,G,B Output Voltage R,G,B Output Load Resistance VOUTC RGB Output Compliance
- - -1.0 - -1.5
- - - - -1.3
1.0 7 0.3 100 -1.2
LSB LSB V V
Referred to VSUPO Ref. to VSUPO Ref. to VSUPO Sum of max. Current of RGBDACs and max. Current of Int. Brightness DACs is 2 % degraded
External RGB Brightness D/A Converter Characteristics Resolution IEXBR Full-Scale Output Current relative Full Scale Output Current absolute Differential Non-Linearity Integral Non-Linearity Matching R-G, R-B, G-B Matching to digital RGB R-R, G-G, B-B ROUT GOUT BOUT - 39.2 - - - -2 -2 9 40 1.5 - - - - - 40.8 - 1 2 2 2 bit % mA LSB LSB % % Ref to max. digital RGB
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DDP 3310B
4.6.4.18. Scan Velocity Modulation Output
Symbol Parameter Resolution IOUT IOUT IOUT IOUT Full-Scale Output Current Differential Non-Linearity Integral Non-Linearity Glitch Pulse Charge Pin Name SVMOUT Min. - 1.55 - - - Typ. 8 1.875 - - 0.5 Max. - 2.25 0.5 1 - Unit bit mA LSB LSB pAs
ADVANCE INFORMATION
Test Conditions
Ramp, output line is terminated on both ends with 50 10 % to 90 %, 90 % to 10 %
IOUT
Rise and Fall Time
-
3
-
ns
4.6.4.19. DAC Reference, Beam Current Safety
Symbol VDACREF Parameter DAC-Ref. Voltage DAC-Ref. Output resistance VXREF DAC-Ref. Voltage Bias Current Generation Pin Name VRD/BCS VRD/BCS XREF Min. 2.38 18 2.25 Typ. 2.50 25 2.34 Max. 2.67 32 2.43 Unit V k V Rxref = 10 k Test Conditions
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Micronas
ADVANCE INFORMATION
DDP 3310B
5. Application Circuit
+5 V
+5 V
+5 V
+5 V
Micronas
+5 V
+5 V
+5 V
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DDP 3310B
ADVANCE INFORMATION
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Micronas
ADVANCE INFORMATION
DDP 3310B
Micronas
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DDP 3310B
6. Data Sheet History 1. Advance Information: "DDP 3310B Display and Deflection Processor, July 9, 1999, 6251-464-1AI. First release of the advance information.
ADVANCE INFORMATION
Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed in Germany Order No. 6251-464-1AI
All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH.
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